Uart2BusTestBench :: Overview
Other project properties
Uart2BusTestBench is implemented using Universal Verification Methodology to perform the functional verification to the RTL design released by Moti Litochevski and Steve MULLER (check this link ).
The Main Features :
- Additional C++ program is attached to facilitate baud frequency calculations.
- Includes UART BFM which in turn act as UART driver and includes all standard routines which makes it possible to bury it into another Testbench (Like UART VIP).
- Includes Register-File BFM which act as slave memory and includes all non-standard routines
- Support inserting idle time between transactions.
You can download The Architecture Specifications from here
|Active Edge||The active clock edge at which, the data is changed on the UART buses||
|First Bit||Represent the sequence through which the byte is serialized||
|Data Mode||The data representation through the text commands||
|Number of stop bits||The number of stop bits sent after the latest bit of each byte||
|Number of bits||The number of bits through each field transfer||
|Parity Mode||The used parity type through each byte||
|Response Time||Represent the maximum allowable time through which dut should respond
to the driven request.