Wishbone LPC Host and Peripheral Bridge :: Bugtracker
Bug(s)
| Date | Title | Status | Assigned to | Submitted by |
| Jan 31, 2012 | wishbone byte strobe handling | OPENED | adyer | |
| Jan 31, 2012 | host SYNC error handling | OPENED | adyer | |
| Jan 24, 2012 | LPC_ST_P_TAR2 and LPC_ST_WB_RETIRE have same value | OPENED | adyer | |
| Nov 3, 2009 | The LPC peripheral should never drive the BUS during LPC_ST_H_TAR2 state | OPENED | jbouchat | |
| Nov 3, 2009 | The LPC peripheral doesn't handle "abort" command | OPENED | jbouchat | |
| Jul 8, 2009 | Quartus v8.1 synthesis problem | OPENED | hharte | tcdev |
| Dec 24, 2008 | Serirq: incorrect stop frame | CLOSED | hharte | hharte |
| Aug 4, 2008 | LPC Peripheral illegaly drives the bus during TAR | OPENED | hharte | danielpreda |
| Jul 28, 2008 | LPC Host does not end a DMA WORD cycle upon Ready response | OPENED | hharte | danielpreda@opencores.org |
| Jul 25, 2008 | LPC firmware writes must not insert wait-states. | CLOSED | hharte | hharte |
| Jul 22, 2008 | LPC DMA does not report READY+MORE for multi-byte transfers | CLOSED | hharte | hharte |
| Jul 22, 2008 | Spec violation for multi-byte firmware accesses | CLOSED | hharte | hharte |
Idea(s)
| Date | Title | Status | Assigned to | Submitted by |
| Jul 23, 2008 | propagate Wishbone errors across LPC interface | CLOSED | hharte | hharte |