OpenCores

PWM Audio Controller :: Overview

Project maintainers

Details

Name: wbpwmaudio
Created: Mar 22, 2016
Updated: May 2, 2016
SVN Updated: May 2, 2016
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Other
Language: Verilog
Development status: Alpha
Additional info: FPGA proven
WishBone compliant: Yes
WishBone version: n/a
License: GPL

Description

This is a very simple PWM audio controller with an integrated timer. It has been designed for use with Digilent's Audio Amplifier, and the current version works quite well with that amplifier as part of the S6Soc project. It has only a one sample buffer, and when the buffer is empty the controller raises an interrupt line for some other logic to refill it again. The controller can either be configured for a fixed audio sample frequency, such as 8kHz, 16kHz, or even 44.1 kHz, or it can be configured to have any audio sample frequency that is an integer divisor of your FPGA's clock rate.

What makes this PWM controller unique from other controllers is the bitreverse. In most PWM controllers, there is a threshold and a counter. When the counter is less than the threshold, the value will be one, and zero otherwise. In this PWM controller, the counter has been bitreversed. Hence, the halfway value isn't a low frequency square wave but a very high frequency square wave. This has been done to increase audio quality by pushing the PWM artifacts towards higher frequencies where they can be filtered out easier. I'll let your ear be the judge as to whether or not this technique works, works well, or just spectacularly fails. (I think it works quite well, although not perfect.) The good news of the whole technique, though, is that a bit reversal doesn't cost anything within an FPGA--so this novel approach doesn't cost anything more than any other PWM technique.

Current Status

This PWM core is simple, and works nicely. All that's missing at this point is a nicely written specification file to bring it to a beta development status. Until then, you'll find quite a few comments within the Verilog file itself (the project is really quite simple ...).

© copyright 1999-2017 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.