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Ethernet 10GE Low Latency MAC :: Overview

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Details

Name: xge_ll_mac
Created: Nov 15, 2012
Updated: Feb 1, 2016
SVN Updated: Dec 1, 2012
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Communication controller
Language: Verilog
Development status: Stable
Additional info: none
WishBone compliant: No
WishBone version: n/a
License: LGPL

Description

This is a fork of the xge_mac and was released by the Computer Architecture Group (http://cag.uni-hd.de) of the University of Heidelberg.

Main changes in this fork:
-Unwanted FIFOs removed
-Latency reduced due to the removal of the FIFOs and a new CRC implementation
-Interface very similar to the one of the Xilinx MAC

This core is in production use.

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