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*Ethernet 10GE MAC :: News

News

Nov 26, 2012 Timing improvements. Reduced FIFO size from 1024 to 512 bytes
Nov 25, 2012 Added basic packet statistics
Nov 24, 2012 Update comments
Nov 23, 2012 Improved design for timing, eliminating chained adders
Nov 23, 2012 Added alternate FIFO design for Xilinx
Feb 17, 2012 Added release notes
Feb 8, 2012 Update feature list
Feb 8, 2012 Updates for Xilinx synthesis
Jan 19, 2012 Added latency numbers to feature list
Aug 21, 2011 Updates to future devel.
Dec 13, 2009 New SERDES examples to 10GE MAC
Jun 7, 2008 Changes commited to CVS
May 19, 2008 Project started
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