YAC - Yet Another CORDIC Core :: Overview
Other project properties
CORDIC is the acronym for COordinate Rotation DIgital Computer and allows a hardware efficient calculation of various functions like
- atan, sin, cos
- atanh, sinh, cosh,
- division, multiplication.
Hardware efficient means, that only shifting, additions and substractions in combination with table-lookup is required. This makes it suitable for a realization in digital hardware. Good introductions can be found in .
The following six CORDIC modes are supported:
- trigonometric rotation
- trigonometric vectoring
- linear rotation
- linear vectoring
- hyperbolic rotation
- hyperbolic vectoring
Furthermore, the CORDIC algorithm is implemented for iterative processing which means, that the IP-core is started with a set of input data and after a specific amount of clock cycles, the result is available. No parallel data can be processed.
In addition to an IP-core written in VHDL, a bit-accurate C-model is provided. This C-model can be compiled as mex for a usage with Octave or Matlab. Therefore, this C-model allows a bit-accurate analysis of the CORDIC performance on a higher level.
- C-model implementation is done
- RTL model implementation is done
- RTL model is verified against C-model
The next steps are
- Add YAC to a FPGA based System-on-Chip to prove FPGA feasibility
- Circuit optimizations
- Numerical optimizations
and the future plans are
- Hyperbolic range extension
- Floating point CORDIC
 Andraka, Ray; A survey of CORDIC algorithms for FPGA based computers, 1989
 Hu, Yu Hen; CORDIC-Based VLSI Architectures for Digital Signal Processing, 1992
 CORDIC on wikibook: http://en.wikibooks.org/wiki/Digital_Circuits/CORDIC
 CORDIC on wikipedia:http://en.wikipedia.org/wiki/CORDIC
 David, Herbert; Meyr, Heinricht; CORDIC Algorithms and Architectures http://www.eecs.berkeley.edu/newton/Classes/EE290sp99/lectures/ee290aSp996_1/cordic_chap24.pdf