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ZAP :: Overview

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Details

Name: zap
Created: Apr 30, 2017
Updated: May 17, 2017
SVN Updated: May 23, 2017
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Processor
Language: Verilog
Development status: Alpha
Additional info: Design done, Specification done
WishBone Compliant: Yes
License: GPL

Latest Version

git clone https://github.com/krevanth/ZAP.git

Overview

ZAP : An ARMv4T core with cache and MMU

Description

ZAP : An open source ARMv4T processor with cache and MMU
Author : Revanth Kamaraj (revanth91kamaraj@gmail.com)
License : GPL v2

All development will be done on Github...
https://github.com/krevanth/ZAP

Description
===================
ZAP is a pipelined ARM processor core that can execute the ARMv4T instruction set. It is equipped with ARMv4 compatible split writeback caches and memory management capabilities. ARMv4 and Thumbv1 instruction sets are supported. The processor core uses a 10 stage pipeline.

Current Status
===================
Experimental

Bus Interface
===================
Wishbone B3 compatible 32-bit bus.

Features
===================
Fully synthesizable Verilog-2001 core
Dual port register file to allow LDR with writeback to execute as a single instruction.
Can execute 32-bit ARMv4 and 16 bit Thumb v1 code(EXPERIMENTAL).
Wishbone B3 32-bit compatible interface. Cache unit supports burst access.
10-stage pipeline design.
Branch prediction is supported.
Split I and D writeback cache (Size can be configured using parameters).
Split I and D MMUs (TLB size can be configured using parameters).
Base restored abort model to simplify abort handling.

Pipeline Overview
===================
FETCH => THUMB_DECODER => FIFO => PRE-DECODE => DECODE => ISSUE => SHIFTER => ALU => MEMORY => WRITEBACK
The pipeline is fully bypassed to allow most dependent instructions to execute without stalls. The pipeline stalls for 3 cycles if there is an attempt to use a value loaded from memory immediately following it. 32x32+32=32 operations take 6 clock cycles while 32x32+64=64 takes 12 clock cycles. Multiplication and non trivial shifts require registers a cycle early else the pipeline stalls for 1 cycle.

Project Documentation
=====================
Please see the docs folder.

To simulate using Icarus Verilog
================================
Enter hw/sim and run run_sim_gui.pl. The command will run the factorial test case (see sw/factorial). Ensure that you have GTKWave installed at your site.

License
=================================
Copyright (C) 2016, 2017 Revanth Kamaraj.

This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.

This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.

You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.

Bugs

- Thumb v1 support is unverified.

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