部分翻译
News
| Aug 23, 2011 |
slight update main page status with FPGA board test-fixture adapters info |
| Aug 22, 2011 |
yet another "nothing yet" status, I've not had free time recently |
| May 6, 2011 |
Subphases for phase2, who needs Autoconfig IDs or not, consider two bridges, one for each direction (Z->WB, WB->Z) rather than one bidirectional bridge. |
| May 6, 2011 |
description update - need to verify the PCB adaptors I imagine can be made, depends on Spartan3 board signal groupings to PCI connector. Update phase 1 to 1a and 1b. Similar sub-phases will likely come for others too. |
| Apr 30, 2011 |
in looking at Minimig/TG68 and aoocs projects, I see that minimig/TG68 are 16bit 68k bus and aoocs is 32bit Wishbone bus. So I guess I need to think more about various bus width bridging. I hadn't thought about that much before, I guess just thinking of Wishbone being 32bit for me, and not realizing that Minimig is 16bit on that side. Hrm. Sure, there's teh 68k/dragonball to Wishbone bridge on OC, but that's only good for a 16bid WB bus too. So I guess I need to think about a new bridge to 32bit WB, or have a look around if there's any existing WB-WB bridges for bus adaptions and have a possibly long chain of bridges together. Or to make Minimig 32bit, whihc would likely be a ton of work, or perhaps the MinimigAGA will already do that when released. Eh, I wish I had more free time. :) |
| Apr 8, 2011 |
I've gradually been studying Zorro2 and Wishbone specs. Time is little and things seem to take forever, but I haven't forgotten. |
| Apr 7, 2011 |
added link to aoOCS as a likely test platform |
| Oct 23, 2010 |
linked to Timing Truetype font for timing diagram editing in docs |
| Sep 7, 2010 |
Decision to license documentation under LGPL instead of GFDL, to be able to derive docs from design/environment sources if that comes up. |
| Jun 30, 2010 |
Changed Wishbone side from B3 to B4, as the B4 spec was just released. |
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