ZPUino :: Overview
Created: Apr 8, 2011
Updated: Apr 9, 2011
SVN: No files checked in
Other project properties
ZPUino is a SoC (System-on-a-Chip) based on Zylin's ZPU 32-bit processor core.
Hardware-wise, ZPUino currently integrates the following devices:
* ZPU Premium Core, a modified ZPU core
* One UART
* Two SPI interfaces
* Two 16-bit timers
* One TSC (Time Stamp Counter)
* 128-bit GPIO interface
* Interrupt Controller
* Two SigmaDelta outputs
* Peripheral Pin Select (optional)
Software-wise, it supports the following features:
* 4Kb Bootloader, which includes required emulation code for ZPU.
* Bootstraps code from program flash (shadows into FPGA blockram)
* Serial programming of program flash.
Where does it run ?
First implementation was done on Spartan3E 500 (-4), on a S3E Starter Kit, with a M25P16 SPI flash ROM and 32Kbytes RAM.
Right now it runs on other boards, see Reference for more information.
Running speed: up to 100MHz, 96MHz recommended
More information and downloads at http://www.alvie.com/zpuino/