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McAdam's RISC Computer Architecture: Overview Details Name: marca Created: 01-Feb-2007 22:54:17 Updated: 02-Feb-2007 16:48:29 CVS: browse Other project properties Category :: Microprocessor Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Production/Stable Project maintainers Wolfgang Puffitsch Statistics view Description McAdam's RISC Computer Architecture (marca) is a simple 16-bit microprocessor, implementing a load/store instruction set architecture and featuring a 4-stage pipeline. Features 16 16-bit registers Harvard architecture all memories on-chip 16KB instruction ROM 8KB data RAM 256 byte data ROM load/store instruction set architecture 75 instructions 16 interrupt vectors 4-stage pipeline Status running on an Altera Cyclone FPGA