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OpenRISC 1000: OpenRISC 1200
Introduction
The aim of this project is to design and maintain an OpenRISC 1200 IP Core. OpenRISC 1200 is an implementation of OpenRISC 1000 processor family. The OR1200 is a 32-bit scalar RISC with Harvard microarchitecture, 5 stage integer pipeline, virtual memory support (MMU) and basic DSP capabilities.
Default caches are 1-way direct-mapped 8KB data cache and 1-way direct-mapped 8KB instruction cache, each with 16-byte line size. Both caches are physically tagged. By default MMUs are implemented and they are constructed of 64-entry hash based 1-way direct-mpped data TLB and 64-entry hash based 1-way direct-mapped instruction TLB. Supplemental facilities include debug unit for real-time debugging, high resolution tick timer, programmable interrupt controller and power management support. When implemented in a worst-case 0.18u 6LM process it should provide over 150 dhrystone 2.1 MIPS at 150MHz and 150 DSP MAC 32x32 operations, at least 20% more than any other competitor in this class (typical corner 250MHz). The default OR1200 configuration is about 40k ASIC gates. Download OpenRISC 1200 IP Core Overview (PDF, 15KB) flyer.
General Microarchitecture
- Central CPU/DSP block
- Direct mapped data cache
- Direct mapped instruction cache
- Data MMU based on hash-based DTLB
- Instruction MMU based on hash-based ITLB
- Power management unit and power management interface
- Tick timer
- Debug unit and development interface
- Interrupt controller and interrupt interface
- Instruction and Data WISHBONE interfaces
Status
RTL coding is finished and is being tested in different test applications including the MP3 player and uclinux port demo. It has also been implemented in various ASICs - for example Flextronics Marvin SOC/ASIC If you would like to help with the development, please contact the developers.
Download
Source code for current development tarball of the OpenRISC 1200 is available from the OpenCores CVS under the module hierarchy or1k/or1200. You can also get it directly by using the CVSget.
Preliminary Results
Synthesis for Virtex FPGA results in a 3000 slices design running at 33MHz and Altera Stratix II 100 MHz (configuration with QMEM and no caches/MMUs).
Synthesis for 0.18u UMC using Virtual Silicon libraries produces 25000 gates design with area of 0.5mm2. Post layout worst case timing is 150MHz.
Documentation
Specification document for OpenRISC 1200 is available both in Adobe PDF form and in MS Word form:
OpenRISC 1200 IP Core Design Document is not yet available. Also see architecture documentation. Tutorials how to implement OR1200 on Altera FPGA and Xilinx FPGA. Credits go to Resarch Group Digital Techniques, Hogeschool voor Wetenschap & Kunst, Campus de Nayer:
Wish List (TODO List)
This is what we would like to develop/see developed but presently nobody is working on these projects. If you want to help, send an email to the mailing list. - Add multiple associativity to cache and MMU
- Optimize for speed, area and power
- Test OR1200 in your applications
- Write design document
If you have a suggestion for new Wish List entry, feel free to send it to the mailing list so that is added to the list and somebody may start working on it.
Mailing List / Discussion Forum
To participate in the development or simply to discuss OpenRISC 1200 issues and to report bugs, go to the openrisc mailing list. To subscribe to the list, follow mailing list subscribe instructions.
Page Maintainer
This web page is maintained by Damjan Lampret
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