Overview :: News :: Architecture :: OpenRISC 1200 :: VMware image :: NEW GNU Toolchain Port :: Architectural Simulator :: U-Boot :: Linux :: uClinux :: RTEMS :: ATS :: ORP :: ORPmon :: ORPsoc :: Survey :: Forum :: Silicon :: Downloads :: Tracker

OpenRISC 1000: Survey OpenRISC Survey Please take a moment to complete this brief, confidential survey. This survey should take less than five minutes and will guide developers to develop and extend the OpenRISC in the right direction. If you don't know or don't want to fill out a particular entry, just leave it blank. Information about you First & Last Name:    Email:                      Organization Name: Organization URL:    Anything else you want to tell us about you or your organization: Current experience with OpenRISC Tell us your current experience with OpenRISC technology. Have you studied OpenRISC 1000 architecture? yes - thoroughly just a quick glimpse no - not at all If yes, in terms of processing performance, how would you rate it from 1 to 10 (10 means excellent)? 12345678910 excellent If yes, in terms of ease of use, how would you rate it from 1 to 10 (10 means excellent)? 12345678910 excellent If yes, in terms of software portability, how would you rate it from 1 to 10 (10 means excellent)? 12345678910 excellent If yes, in terms of extendability & customization, how would you rate it from 1 to 10 (10 means excellent)? 12345678910 excellent If you rate features of OpenRISC 1000, what are the most important features for you at the moment? open free 32-bit integer (ORBIS 32) 64-bit integer (ORBIS 64) floating-point extension vector extension DSP extension virtual memory shadow contexts Other - Do you already use OR1200 RTL in a project? yes no planning to Description or URL of your project/product? What units of OpenRISC architecture implemented in OR1200 are important to you? CPU MMU Cache Interrupt Cntrl Tick Timer Power Mngmt Debug DSP/MAC Other - How did you implement OR1200? 1. Target Technology: FPGA Gate Array Std Cell Custom Other - 2. Simulation Tool Vendor: FPGA vendor Cadence Synopsys Mentor Other - 3. Synthesis Tool Vendor: FPGA vendor Cadence Synplicity Synopsys Mentor Other - 4. Layout Tool Vendor: FPGA vendor Cadence Avanti Other - 5. FPGA: Xilinx Virtex/VirtexII family Altera Apex/ApexII family Xilinx SpartanII family Altera Acex family Altera Stratix family Other - 6. IC Library Vendors: Virtual Silicon Artisan Other - 7. IC Foundaries: UMC TSMC IBM Chartered Other - 8. IC Geometry: 0.5u+ 0.35u 0.25u 0.18u 0.13u 0.09u- Other - What are important advantages of OR1200 RTL for your project/product? What is OR1200 clock frequency in your project/product? What is OR1200 size in your project/product? Have you used any other OpenCores IPs in your project/product? yes -       no Did/would you have to modify OR1200 to fit your needs? Yes - significantly Very little No - it fitted perfectly Are you satisfied with WISHBONE bus as OR1200 main SOC interconnect? yes no If not, what other inerconnect bus you want? AMBA CoreConnect Avalon Other - Have you evaluated OR1200 RTL and how? yes -       no Have you evaluated OpenRISC GNU Toolchain (compiler, debugger)? yes no Have you evaluated OpenRISC simulator? yes no Have you evaluated OpenRISC uClinux port? yes Have you evaluated OpenRISC RTEMS port? yes no If you did (some) evaluation, were you satisfied with evaluation? What impressed you the most? What disappointed you the most? What would you be your overall rating of entire OpenRISC project, from 1 to 10 (10 means excellent)? 12345678910 excellent Do you plan to use OpenRISC in your project/product in the future? yes maybe no If maybe or no, what needs to be changed in OpenRISC so that you use it in your prodjct/product? What do you consider the most important advantages of OR1200 RTL? open source free of charge technical aspects Other -       Future What is for you important in the future. Where do you want development to go? What units of OpenRISC architecture should be implemented in implementations? RISC CPU DSP MMU Cache Interrupt Cntrl Tick Timer Power Mngmt Debug Floating Point Vector Unit Other -       What features of implementations are the most important to you? Scalar (less processing performance - 1 insn/clock cycle, smaller design,less power consumption) Superscalar (More processing performance - many insns/clock cycle, bigger design, more power consumption) Reduced power consumption Reduced integration complexity Slower yet simple register file Slower single clock edge Synchronous design Faster, time borrowing dual clock edge Synchronous design Very fast, complex asynchrnous/synchronous design Floating point unit Vector unit DSP unit Other -       What should be target speed of low performance, small OpenRISC implementations (specify technology)? What should be power consumption of low performance, small OpenRISC implementations (specify technology)? What should be size of low performance, small OpenRISC implementations (specify technology)? What should be target speed of high performance, large OpenRISC implementations (specify technology)? What should be power consumption of high performance, large OpenRISC implementations (specify technology)? What should be size of high performance, large OpenRISC implementations (specify technology)? What target technology is important to you for OpenRISC implementations? 1. Target Technology: FPGA Gate Array GStd Cell Custom Other - 2. Simulation Tool Vendor: FPGA vendor Cadence Synopsys Mentor Other - 3. Synthesis Tool Vendor: FPGA vendor Cadence Synplicity Synopsys Mentor Other - 4. Layout Tool Vendor: FPGA vendor Cadence Avanti Other - 5. FPGA: Xilinx Virtex/VirtexII family Altera Apex/ApexII family Xilinx SpartanII family Altera Acex family Altera Stratix family Other - 6. IC Library Vendors: Virtual Silicon Artisan Other - 7. IC Foundaries: UMC TSMC IBM Chartered Other - 8. IC Geometry: 0.5u+ 0.35u 0.25u 0.18u 0.13u 0.09u- Other - Do you see OpenRISC software incompatibility with other processor architectures (ARM, MIPS, x86) as a major issue? yes no If yes, do you consider using a different processor architecture because of software incompatibility, which one? yes - no Should OpenRISC implementations be able to support other ISAs, which one? yes -     ARM     MIPS     SPARC     x86     Other - no If OpenRISC implementations should not support other ISAs, why not? What advantages do you see not supporting other ISAs? SPARC architecture unlike ARM/MIPS is open, would you prefer to chose SPARC implementation over OpenRISC implementation? yes no What other features OpenRISC architecture is missing? What other features OpenRISC implementations are missing? What applications OpenRISC implementations are suitable for? ASICs ASSPs Other - Are open source ports of uClinux and RTEMS OSes enough? yes no If no, what other open source OS ports are needed? Linux eCos Other - If no, what other proprietary OS ports are needed? VxWorks Windows CE Other - Should OpenRISC GNU toolchain be tested on other platforms than Linux? yes no If yes, what other platforms? Solaris HP-UX MS Windows Should OpenRISC tools have graphical user interfaces? yes - simulator needs GUI, entire toolchain IDE is needed no - DDD for debugger is enough Should OpenRISC implementations be configurable also via a GUI as opposed to currently a defines.v file? yes no Should OpenRISC implementations be available also in VHDL as opposed to only Verilog at the moment? yes - more important than Verilog maybe - if you have time to port it no - Verilog is enough Anything else you want to tell us?