| Memory core | ||||
| Project | Files | Statistics | Status | License |
| Asynchronous... |
|
Stats | GPL | |
| CF Interleaver |
|
Stats | ||
| DDR SDRAM Controller Core |
|
Stats | ||
| DirectMappedCacheController |
|
Stats | LGPL | |
| Functional simulation models... |
|
Stats |
|
LGPL |
| Generic FIFOs |
|
Stats | ||
High Performance Dynamic...
|
|
Stats |
|
GPL |
| High Speed SDRAM Controller... |
|
Stats |
|
|
| Memory cores |
|
Stats | ||
| Memory sizer |
|
Stats |
|
|
| memory stealer |
|
Stats |
|
LGPL |
| NAND Flash Controller |
|
Stats | LGPL | |
| OPB PSRAM Controller |
|
Stats | GPL | |
| Open FreeList |
|
Stats | LGPL | |
| Parameterisable DRAM model |
|
Stats | ||
| Parametrized FIFO based on... |
|
Stats |
|
LGPL |
| RAM_wb |
|
Stats |
|
LGPL |
| Scratch DDR SDRAM Controller |
|
Stats | LGPL | |
| Single Port ASRAM |
|
Stats | ||
| sp_ram to 3p_ram WISHBONE... |
|
Stats |
|
LGPL |
| srl_fifo |
|
Stats |
|
LGPL |
| SSRAM interface |
|
Stats | ||
| Versatile FIFO |
|
Stats | LGPL | |
| Versatile memory controller |
|
Stats |
|
LGPL |
| wb_async_mem_bridge |
|
Stats |
|
LGPL |
| wb_ddr: Asynchronous DDR... |
|
Stats |
|
LGPL |
| wb_size_bridge |
|
Stats |
|
|
| Wishbone FLASH Interface for... |
|
Stats |
|
LGPL |
| ZBT SRAM Controller |
|
Stats |
|
|