OpenCores
URL https://opencores.org/ocsvn/fpu/fpu/trunk

Subversion Repositories fpu

[/] [fpu/] [trunk/] [verilog/] [fpu.v] - Blame information for rev 11

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 rudi
/////////////////////////////////////////////////////////////////////
2
////                                                             ////
3
////  FPU                                                        ////
4
////  Floating Point Unit (Single precision)                     ////
5
////                                                             ////
6
////  Author: Rudolf Usselmann                                   ////
7
////          rudi@asics.ws                                      ////
8
////                                                             ////
9
/////////////////////////////////////////////////////////////////////
10
////                                                             ////
11
//// Copyright (C) 2000 Rudolf Usselmann                         ////
12
////                    rudi@asics.ws                            ////
13
////                                                             ////
14
//// This source file may be used and distributed without        ////
15
//// restriction provided that this copyright statement is not   ////
16
//// removed from the file and that any derivative work contains ////
17
//// the original copyright notice and the associated disclaimer.////
18
////                                                             ////
19
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
20
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
21
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
22
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
23
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
24
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
25
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
26
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
27
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
28
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
29
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
30
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
31
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
32
////                                                             ////
33
/////////////////////////////////////////////////////////////////////
34
 
35
`timescale 1ns / 100ps
36
 
37
/*
38
 
39
FPU Operations (fpu_op):
40
========================
41
 
42
 
43
1 = sub
44
2 = mul
45
3 = div
46
4 =
47
5 =
48
6 =
49
7 =
50
 
51
Rounding Modes (rmode):
52
=======================
53
 
54
 
55
1 = round_to_zero
56
2 = round_up
57
3 = round_down
58
 
59
*/
60
 
61
 
62
module fpu( clk, rmode, fpu_op, opa, opb, out, inf, snan, qnan, ine, overflow, underflow, zero, div_by_zero);
63
input           clk;
64
input   [1:0]    rmode;
65
input   [2:0]    fpu_op;
66
input   [31:0]   opa, opb;
67
output  [31:0]   out;
68
output          inf, snan, qnan;
69
output          ine;
70
output          overflow, underflow;
71
output          zero;
72
output          div_by_zero;
73
 
74
parameter       INF  = 31'h7f800000,
75
                QNAN = 31'h7fc00001,
76
                SNAN = 31'h7f800001;
77
 
78
////////////////////////////////////////////////////////////////////////
79
//
80
// Local Wires
81
//
82
reg             zero;
83
reg     [31:0]   opa_r, opb_r;           // Input operand registers
84
reg     [31:0]   out;                    // Output register
85
reg             div_by_zero;            // Divide by zero output register
86
wire            signa, signb;           // alias to opX sign
87
wire            sign_fasu;              // sign output
88
wire    [26:0]   fracta, fractb;         // Fraction Outputs from EQU block
89
wire    [7:0]    exp_fasu;               // Exponent output from EQU block
90
reg     [7:0]    exp_r;                  // Exponent output (registerd)
91
wire    [26:0]   fract_out_d;            // fraction output
92
wire            co;                     // carry output
93
reg     [27:0]   fract_out_q;            // fraction output (registerd)
94
wire    [30:0]   out_d;                  // Intermediate final result output
95
wire            overflow_d, underflow_d;// Overflow/Underflow Indicators
96
reg             overflow, underflow;    // Output registers for Overflow & Underflow
97
reg             inf, snan, qnan;        // Output Registers for INF, SNAN and QNAN
98
reg             ine;                    // Output Registers for INE
99
reg     [1:0]    rmode_r1, rmode_r2,     // Pipeline registers for rounding mode
100
                rmode_r3;
101
reg     [2:0]    fpu_op_r1, fpu_op_r2,   // Pipeline registers for fp opration
102
                fpu_op_r3;
103
wire            mul_inf, div_inf;
104
wire            mul_00, div_00;
105
 
106
////////////////////////////////////////////////////////////////////////
107
//
108
// Input Registers
109
//
110
 
111
always @(posedge clk)
112
        opa_r <= #1 opa;
113
 
114
always @(posedge clk)
115
        opb_r <= #1 opb;
116
 
117
always @(posedge clk)
118
        rmode_r1 <= #1 rmode;
119
 
120
always @(posedge clk)
121
        rmode_r2 <= #1 rmode_r1;
122
 
123
always @(posedge clk)
124
        rmode_r3 <= #1 rmode_r2;
125
 
126
always @(posedge clk)
127
        fpu_op_r1 <= #1 fpu_op;
128
 
129
always @(posedge clk)
130
        fpu_op_r2 <= #1 fpu_op_r1;
131
 
132
always @(posedge clk)
133
        fpu_op_r3 <= #1 fpu_op_r2;
134
 
135
////////////////////////////////////////////////////////////////////////
136
//
137
// Exceptions block
138
//
139
wire            inf_d, ind_d, qnan_d, snan_d, opa_nan, opb_nan;
140
wire            opa_00, opb_00;
141
wire            opa_inf, opb_inf;
142
wire            opa_dn, opb_dn;
143
 
144
except u0(      .clk(clk),
145
                .opa(opa_r), .opb(opb_r),
146
                .inf(inf_d), .ind(ind_d),
147
                .qnan(qnan_d), .snan(snan_d),
148
                .opa_nan(opa_nan), .opb_nan(opb_nan),
149
                .opa_00(opa_00), .opb_00(opb_00),
150
                .opa_inf(opa_inf), .opb_inf(opb_inf),
151
                .opa_dn(opa_dn), .opb_dn(opb_dn)
152
                );
153
 
154
////////////////////////////////////////////////////////////////////////
155
//
156
// Pre-Normalize block
157
// - Adjusts the numbers to equal exponents and sorts them
158
// - determine result sign
159
// - determine actual operation to perform (add or sub)
160
//
161
 
162
wire            nan_sign_d, result_zero_sign_d;
163
reg             sign_fasu_r;
164
wire    [7:0]    exp_mul;
165
wire            sign_mul;
166
reg             sign_mul_r;
167
wire    [23:0]   fracta_mul, fractb_mul;
168
wire            inf_mul;
169
reg             inf_mul_r;
170
wire    [1:0]    exp_ovf;
171
reg     [1:0]    exp_ovf_r;
172
wire            sign_exe;
173
reg             sign_exe_r;
174
wire    [2:0]    underflow_fmul_d;
175
 
176
 
177
pre_norm u1(.clk(clk),                          // System Clock
178
        .rmode(rmode_r2),                       // Roundin Mode
179
        .add(!fpu_op_r1[0]),                     // Add/Sub Input
180
        .opa(opa_r),  .opb(opb_r),              // Registered OP Inputs
181
        .opa_nan(opa_nan),                      // OpA is a NAN indicator
182
        .opb_nan(opb_nan),                      // OpB is a NAN indicator
183
        .fracta_out(fracta),                    // Equalized and sorted fraction
184
        .fractb_out(fractb),                    // outputs (Registered)
185
        .exp_dn_out(exp_fasu),                  // Selected exponent output (registered);
186
        .sign(sign_fasu),                       // Encoded output Sign (registered)
187
        .nan_sign(nan_sign_d),                  // Output Sign for NANs (registered)
188
        .result_zero_sign(result_zero_sign_d),  // Output Sign for zero result (registered)
189
        .fasu_op(fasu_op)                       // Actual fasu operation output (registered)
190
        );
191
 
192
always @(posedge clk)
193
        sign_fasu_r <= #1 sign_fasu;
194
 
195
pre_norm_fmul u2(
196
                .clk(clk),
197
                .fpu_op(fpu_op_r1),
198
                .opa(opa_r), .opb(opb_r),
199
                .fracta(fracta_mul),
200
                .fractb(fractb_mul),
201
                .exp_out(exp_mul),      // FMUL exponent output (registered)
202
                .sign(sign_mul),        // FMUL sign output (registered)
203
                .sign_exe(sign_exe),    // FMUL exception sign output (registered)
204
                .inf(inf_mul),          // FMUL inf output (registered)
205
                .exp_ovf(exp_ovf),      // FMUL exponnent overflow output (registered)
206
                .underflow(underflow_fmul_d)
207
                );
208
 
209
 
210
always @(posedge clk)
211
        sign_mul_r <= #1 sign_mul;
212
 
213
always @(posedge clk)
214
        sign_exe_r <= #1 sign_exe;
215
 
216
always @(posedge clk)
217
        inf_mul_r <= #1 inf_mul;
218
 
219
always @(posedge clk)
220
        exp_ovf_r <= #1 exp_ovf;
221
 
222
 
223
////////////////////////////////////////////////////////////////////////
224
//
225
// Add/Sub
226
//
227
 
228
add_sub27 u3(
229
        .add(fasu_op),                  // Add/Sub
230
        .opa(fracta),                   // Fraction A input
231
        .opb(fractb),                   // Fraction B Input
232
        .sum(fract_out_d),              // SUM output
233
        .co(co_d) );                    // Carry Output
234
 
235
always @(posedge clk)
236
        fract_out_q <= #1 {co_d, fract_out_d};
237
 
238
////////////////////////////////////////////////////////////////////////
239
//
240
// Mul
241
//
242
wire    [47:0]   prod;
243
 
244
mul_r2 u5(.clk(clk), .opa(fracta_mul), .opb(fractb_mul), .prod(prod));
245
 
246
////////////////////////////////////////////////////////////////////////
247
//
248
// Divide
249
//
250
wire    [49:0]   quo;
251
wire    [49:0]   fdiv_opa;
252
wire    [49:0]   remainder;
253
wire            remainder_00;
254
reg     [4:0]    div_opa_ldz_d, div_opa_ldz_r1, div_opa_ldz_r2;
255
 
256
always @(fracta_mul)
257
        casex(fracta_mul[22:0])
258
           23'b1??????????????????????: div_opa_ldz_d = 1;
259
           23'b01?????????????????????: div_opa_ldz_d = 2;
260
           23'b001????????????????????: div_opa_ldz_d = 3;
261
           23'b0001???????????????????: div_opa_ldz_d = 4;
262
           23'b00001??????????????????: div_opa_ldz_d = 5;
263
           23'b000001?????????????????: div_opa_ldz_d = 6;
264
           23'b0000001????????????????: div_opa_ldz_d = 7;
265
           23'b00000001???????????????: div_opa_ldz_d = 8;
266
           23'b000000001??????????????: div_opa_ldz_d = 9;
267
           23'b0000000001?????????????: div_opa_ldz_d = 10;
268
           23'b00000000001????????????: div_opa_ldz_d = 11;
269
           23'b000000000001???????????: div_opa_ldz_d = 12;
270
           23'b0000000000001??????????: div_opa_ldz_d = 13;
271
           23'b00000000000001?????????: div_opa_ldz_d = 14;
272
           23'b000000000000001????????: div_opa_ldz_d = 15;
273
           23'b0000000000000001???????: div_opa_ldz_d = 16;
274
           23'b00000000000000001??????: div_opa_ldz_d = 17;
275
           23'b000000000000000001?????: div_opa_ldz_d = 18;
276
           23'b0000000000000000001????: div_opa_ldz_d = 19;
277
           23'b00000000000000000001???: div_opa_ldz_d = 20;
278
           23'b000000000000000000001??: div_opa_ldz_d = 21;
279
           23'b0000000000000000000001?: div_opa_ldz_d = 22;
280
           23'b0000000000000000000000?: div_opa_ldz_d = 23;
281
        endcase
282
 
283
assign fdiv_opa = !(|opa_r[30:23]) ? {(fracta_mul<<div_opa_ldz_d), 26'h0} : {fracta_mul, 26'h0};
284
 
285
 
286
div_r2 u6(.clk(clk), .opa(fdiv_opa), .opb(fractb_mul), .quo(quo), .rem(remainder));
287
 
288
assign remainder_00 = !(|remainder);
289
 
290
always @(posedge clk)
291
        div_opa_ldz_r1 <= #1 div_opa_ldz_d;
292
 
293
always @(posedge clk)
294
        div_opa_ldz_r2 <= #1 div_opa_ldz_r1;
295
 
296
 
297
////////////////////////////////////////////////////////////////////////
298
//
299
// Normalize Result
300
//
301
wire            ine_d;
302 5 rudi
reg     [47:0]   fract_denorm;
303
wire    [47:0]   fract_div;
304 2 rudi
wire            sign_d;
305
reg             sign;
306 5 rudi
reg     [30:0]   opa_r1;
307
reg     [47:0]   fract_i2f;
308
reg             opas_r1, opas_r2;
309
wire            f2i_out_sign;
310 2 rudi
 
311
always @(posedge clk)                   // Exponent must be once cycle delayed
312 5 rudi
        case(fpu_op_r2)
313
          0,1:   exp_r <= #1 exp_fasu;
314
          2,3:  exp_r <= #1 exp_mul;
315
          4:    exp_r <= #1 0;
316
          5:    exp_r <= #1 opa_r1[30:23];
317
        endcase
318 2 rudi
 
319
assign fract_div = (opb_dn ? quo[49:2] : {quo[26:0], 21'h0});
320
 
321 5 rudi
always @(posedge clk)
322
        opa_r1 <= #1 opa_r[30:0];
323 2 rudi
 
324 5 rudi
always @(posedge clk)
325
        fract_i2f <= #1 (fpu_op_r2==5) ?
326
                        (sign_d ?  1-{24'h00, (|opa_r1[30:23]), opa_r1[22:0]}-1 : {24'h0, (|opa_r1[30:23]), opa_r1[22:0]}) :
327
                        (sign_d ? 1 - {opa_r1, 17'h01} : {opa_r1, 17'h0});
328
 
329
always @(fpu_op_r3 or fract_out_q or prod or fract_div or fract_i2f)
330
        case(fpu_op_r3)
331
           0,1:  fract_denorm = {fract_out_q, 20'h0};
332
           2:   fract_denorm = prod;
333
           3:   fract_denorm = fract_div;
334
           4,5: fract_denorm = fract_i2f;
335
        endcase
336
 
337
 
338
always @(posedge clk)
339
        opas_r1 <= #1 opa_r[31];
340
 
341
always @(posedge clk)
342
        opas_r2 <= #1 opas_r1;
343
 
344 2 rudi
assign sign_d = fpu_op_r2[1] ? sign_mul : sign_fasu;
345
 
346
always @(posedge clk)
347
        sign <= #1 (rmode_r2==2'h3) ? !sign_d : sign_d;
348
 
349
post_norm u4(.clk(clk),                 // System Clock
350
        .fpu_op(fpu_op_r3),             // Floating Point Operation
351 5 rudi
        .opas(opas_r2),                 // OPA Sign
352 2 rudi
        .sign(sign),                    // Sign of the result
353
        .rmode(rmode_r3),               // Rounding mode
354
        .fract_in(fract_denorm),        // Fraction Input
355
        .exp_ovf(exp_ovf_r),            // Exponent Overflow
356
        .exp_in(exp_r),                 // Exponent Input
357
        .opa_dn(opa_dn),                // Operand A Denormalized
358
        .opb_dn(opb_dn),                // Operand A Denormalized
359
        .rem_00(remainder_00),          // Diveide Remainder is zero
360
        .div_opa_ldz(div_opa_ldz_r2),   // Divide opa leading zeros count
361
        .output_zero(mul_00 | div_00),  // Force output to Zero
362
        .out(out_d),                    // Normalized output (un-registered)
363
        .ine(ine_d),                    // Result Inexact output (un-registered)
364
        .overflow(overflow_d),          // Overflow output (un-registered)
365 5 rudi
        .underflow(underflow_d),        // Underflow output (un-registered)
366
        .f2i_out_sign(f2i_out_sign)     // F2I Output Sign
367 2 rudi
        );
368
 
369
////////////////////////////////////////////////////////////////////////
370
//
371
// FPU Outputs
372
//
373
reg             fasu_op_r1, fasu_op_r2;
374
wire    [30:0]   out_fixed;
375
wire            output_zero_fasu;
376
wire            output_zero_fdiv;
377
wire            output_zero_fmul;
378
reg             inf_mul2;
379
wire            overflow_fasu;
380
wire            overflow_fmul;
381
wire            overflow_fdiv;
382
wire            inf_fmul;
383
wire            sign_mul_final;
384
wire            out_d_00;
385
wire            sign_div_final;
386
wire            ine_mul, ine_mula, ine_div, ine_fasu;
387
wire            underflow_fasu, underflow_fmul, underflow_fdiv;
388
wire            underflow_fmul1;
389
reg     [2:0]    underflow_fmul_r;
390
reg             opa_nan_r;
391
 
392
 
393
always @(posedge clk)
394
        fasu_op_r1 <= #1 fasu_op;
395
 
396
always @(posedge clk)
397
        fasu_op_r2 <= #1 fasu_op_r1;
398
 
399
always @(posedge clk)
400
        inf_mul2 <= #1 exp_mul == 8'hff;
401
 
402
 
403
// Force pre-set values for non numerical output
404
assign mul_inf = (fpu_op_r3==3'b010) & (inf_mul_r | inf_mul2) & (rmode_r3==2'h0);
405
assign div_inf = (fpu_op_r3==3'b011) & (opb_00 | opa_inf);
406
 
407
assign mul_00 = (fpu_op_r3==3'b010) & (opa_00 | opb_00);
408
assign div_00 = (fpu_op_r3==3'b011) & (opa_00 | opb_inf);
409
 
410
assign out_fixed = (    (qnan_d | snan_d) |
411
                        (ind_d & !fasu_op_r2) |
412
                        ((fpu_op_r3==3'b011) & opb_00 & opa_00) |
413
                        (((opa_inf & opb_00) | (opb_inf & opa_00 )) & fpu_op_r3==3'b010)
414
                   )  ? QNAN : INF;
415
 
416
always @(posedge clk)
417 5 rudi
        out[30:0] <= #1 (mul_inf | div_inf | (inf_d & (fpu_op_r3!=3'b011) & (fpu_op_r3!=3'b101)) | snan_d | qnan_d) & fpu_op_r3!=3'b100 ? out_fixed :
418 2 rudi
                        out_d;
419
 
420
assign out_d_00 = !(|out_d);
421
 
422
assign sign_mul_final = (sign_exe_r & ((opa_00 & opb_inf) | (opb_00 & opa_inf))) ? !sign_mul_r : sign_mul_r;
423
assign sign_div_final = (sign_exe_r & (opa_inf & opb_inf)) ? !sign_mul_r : sign_mul_r | (opa_00 & opb_00);
424
 
425
always @(posedge clk)
426 5 rudi
        out[31] <= #1   ((fpu_op_r3==3'b101) & out_d_00) ? (f2i_out_sign & !(qnan_d | snan_d) ) :
427
                        ((fpu_op_r3==3'b010) & !(snan_d | qnan_d)) ?    sign_mul_final :
428 2 rudi
                        ((fpu_op_r3==3'b011) & !(snan_d | qnan_d)) ?    sign_div_final :
429
                        (snan_d | qnan_d | ind_d) ?                     nan_sign_d :
430
                        output_zero_fasu ?                              result_zero_sign_d :
431
                                                                        sign_fasu_r;
432
 
433
// Exception Outputs
434
assign ine_mula = ((inf_mul_r |  inf_mul2 | opa_inf | opb_inf) & (rmode_r3==2'h1) &
435
                !((opa_inf & opb_00) | (opb_inf & opa_00 )) & fpu_op_r3[1]);
436
 
437
assign ine_mul  = (ine_mula | ine_d | inf_fmul | out_d_00 | overflow_d | underflow_d) &
438
                  !opa_00 & !opb_00 & !(snan_d | qnan_d | inf_d);
439
assign ine_div  = (ine_d | overflow_d | underflow_d) & !(opb_00 | snan_d | qnan_d | inf_d);
440
assign ine_fasu = (ine_d | overflow_d | underflow_d) & !(snan_d | qnan_d | inf_d);
441
 
442
always @(posedge  clk)
443 5 rudi
        ine <= #1        fpu_op_r3[2] ? ine_d :
444
                        !fpu_op_r3[1] ? ine_fasu :
445
                         fpu_op_r3[0] ? ine_div  : ine_mul;
446 2 rudi
 
447
 
448
assign overflow_fasu = overflow_d & !(snan_d | qnan_d | inf_d);
449
assign overflow_fmul = !inf_d & (inf_mul_r | inf_mul2 | overflow_d) & !(snan_d | qnan_d);
450
assign overflow_fdiv = (overflow_d & !(opb_00 | inf_d | snan_d | qnan_d));
451
 
452
always @(posedge clk)
453 5 rudi
        overflow <= #1   fpu_op_r3[2] ? 0 :
454
                        !fpu_op_r3[1] ? overflow_fasu :
455
                         fpu_op_r3[0] ? overflow_fdiv : overflow_fmul;
456 2 rudi
 
457
always @(posedge clk)
458
        underflow_fmul_r <= #1 underflow_fmul_d;
459
 
460
 
461
assign underflow_fmul1 = underflow_fmul_r[0] |
462
                        (underflow_fmul_r[1] & underflow_d ) |
463
                        ((opa_dn | opb_dn) & out_d_00 & (prod!=0) & sign) |
464
                        (underflow_fmul_r[2] & ((out_d[30:23]==0) | (out_d[22:0]==0)));
465
 
466
assign underflow_fasu = underflow_d & !(inf_d | snan_d | qnan_d);
467
assign underflow_fmul = underflow_fmul1 & !(snan_d | qnan_d | inf_mul_r);
468
assign underflow_fdiv = underflow_fasu & !opb_00;
469
 
470
always @(posedge clk)
471 5 rudi
        underflow <= #1  fpu_op_r3[2] ? 0 :
472
                        !fpu_op_r3[1] ? underflow_fasu :
473 2 rudi
                         fpu_op_r3[0] ? underflow_fdiv : underflow_fmul;
474
 
475
always @(posedge clk)
476
        snan <= #1 snan_d;
477
 
478
// synopsys translate_off
479
wire            mul_uf_del;
480
wire            uf2_del, ufb2_del, ufc2_del,  underflow_d_del;
481
wire            co_del;
482
wire    [30:0]   out_d_del;
483
wire            ov_fasu_del, ov_fmul_del;
484
wire    [2:0]    fop;
485
wire    [4:0]    ldza_del;
486
wire    [49:0]   quo_del;
487
 
488
delay1  #0 ud000(clk, underflow_fmul1, mul_uf_del);
489
delay1  #0 ud001(clk, underflow_fmul_r[0], uf2_del);
490
delay1  #0 ud002(clk, underflow_fmul_r[1], ufb2_del);
491
delay1  #0 ud003(clk, underflow_d, underflow_d_del);
492
delay1  #0 ud004(clk, test.u0.u4.exp_out1_co, co_del);
493
delay1  #0 ud005(clk, underflow_fmul_r[2], ufc2_del);
494
delay1 #30 ud006(clk, out_d, out_d_del);
495
 
496
delay1  #0 ud007(clk, overflow_fasu, ov_fasu_del);
497
delay1  #0 ud008(clk, overflow_fmul, ov_fmul_del);
498
 
499
delay1  #2 ud009(clk, fpu_op_r3, fop);
500
 
501
delay3  #4 ud010(clk, div_opa_ldz_d, ldza_del);
502
 
503
delay1  #49 ud012(clk, quo, quo_del);
504
 
505
always @(test.error_event)
506
   begin
507
        #0.2
508
        $display("muf: %b uf0: %b uf1: %b uf2: %b, tx0: %b, co: %b, out_d: %h (%h %h), ov_fasu: %b, ov_fmul: %b, fop: %h",
509
                        mul_uf_del, uf2_del, ufb2_del, ufc2_del, underflow_d_del, co_del, out_d_del, out_d_del[30:23], out_d_del[22:0],
510
                        ov_fasu_del, ov_fmul_del, fop );
511
        $display("ldza: %h, quo: %b",
512
                        ldza_del, quo_del);
513
   end
514
// synopsys translate_on
515
 
516
 
517
 
518
// Status Outputs
519
always @(posedge clk)
520 5 rudi
        qnan <= #1      fpu_op_r3[2] ? 0 : (
521
                                                snan_d | qnan_d | (ind_d & !fasu_op_r2) |
522
                                                (opa_00 & opb_00 & fpu_op_r3==3'b011) |
523
                                                (((opa_inf & opb_00) | (opb_inf & opa_00 )) & fpu_op_r3==3'b010)
524
                                           );
525 2 rudi
 
526
assign inf_fmul =       (((inf_mul_r | inf_mul2) & (rmode_r3==2'h0)) | opa_inf | opb_inf) &
527
                        !((opa_inf & opb_00) | (opb_inf & opa_00 )) &
528
                        fpu_op_r3==3'b010;
529
 
530
always @(posedge clk)
531 5 rudi
        inf <= #1       fpu_op_r3[2] ? 0 :
532
                        (!(qnan_d | snan_d) & (
533 2 rudi
                                                ((&out_d[30:23]) & !(|out_d[22:0]) & !(opb_00 & fpu_op_r3==3'b011)) |
534
                                                (inf_d & !(ind_d & !fasu_op_r2) & !fpu_op_r3[1]) |
535
                                                inf_fmul |
536
                                                (!opa_00 & opb_00 & fpu_op_r3==3'b011) |
537
                                                (fpu_op_r3==3'b011 & opa_inf & !opb_inf)
538 5 rudi
                                              )
539
                        );
540 2 rudi
 
541
assign output_zero_fasu = out_d_00 & !(inf_d | snan_d | qnan_d);
542
assign output_zero_fdiv = (div_00 | (out_d_00 & !opb_00)) & !(opa_inf & opb_inf) &
543
                          !(opa_00 & opb_00) & !(qnan_d | snan_d);
544
assign output_zero_fmul = (out_d_00 | opa_00 | opb_00) &
545
                          !(inf_mul_r | inf_mul2 | opa_inf | opb_inf | snan_d | qnan_d) &
546
                          !(opa_inf & opb_00) & !(opb_inf & opa_00);
547
 
548
always @(posedge clk)
549 5 rudi
        zero <= #1      fpu_op_r3==3'b101 ?     out_d_00 & !(snan_d | qnan_d):
550
                        fpu_op_r3==3'b011 ?     output_zero_fdiv :
551 2 rudi
                        fpu_op_r3==3'b010 ?     output_zero_fmul :
552
                                                output_zero_fasu ;
553
 
554
always @(posedge clk)
555
        opa_nan_r <= #1 !opa_nan & fpu_op_r2==3'b011;
556
 
557
always @(posedge clk)
558
        div_by_zero <= #1 opa_nan_r & !opa_00 & !opa_inf & opb_00;
559
 
560
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.