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[/] [socgen/] [trunk/] [projects/] [opencores.org/] [io/] [ip/] [io_module/] [rtl/] [xml/] [io_module_gpio.xml] - Blame information for rev 127

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
io
io_module
gpio
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 

 

 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      top.gpio
    
    
      dest_dir
      ../verilog
    
  

 
 

  gen_verilogLib_sim
  105.0
  none
  sim
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
  

 
 
 

 
 

 
   
      fs-common
 
 
      
        
        ../verilog/top.gpio.rtl
        verilogSourcefragment
      
 
   
 
 
   
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top.gpio
        verilogSourcemodule
      
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
   
 
 
   
      fs-syn
 
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
 
 
 
   
 
    
 
      fs-lint
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
 

 
 
 
 
 

       
 
              
              Hierarchical
              
              
                                   spirit:library="io"
                                   spirit:name="io_module"
                                   spirit:version="gpio.designCfg"/>
              
 
              
              common:socgen.opencores.org:
              ::
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:socgen.opencores.org:
              ::
              Verilog
              
                     
                            fs-sim
                     
              
 
 
      
 
 
 

UART_PRESCALE5'b01100
UART_PRE_SIZE5
UART_DIV0
BASE_WIDTH8
ADDR_WIDTH16
NMI_MODE8'h00
IRQ_MODE8'h00
 

 
 
 
 
 

 
 
 
enable
wire
in

 
 
 
 
wait_n
wire
out

 
 
gpio_0_out
wire
out
70

 
gpio_0_oe
wire
out
70

 
 
gpio_0_in
wire
in
70

 
gpio_1_out
wire
out
70

 
gpio_1_oe
wire
out
70

 
 
 
gpio_1_in
wire
in
70

 
timer_irq
wire
out
10

 
pic_irq
wire
out

 
pic_nmi
wire
out

 
pic_irq_in
wire
in
70

 
 
cts_pad_in
wire
in

 
rts_pad_out
wire
out

 
rx_irq
wire
out

 
tx_irq
wire
out

 

 
 

 
 
 
 
 
 

 
 
 
 
 

Line No.	Rev	Author	Line
1	99	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32	125	jt_eaton	`xmlns:socgen="http://opencores.org"`
33	99	jt_eaton	`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`io`
39			`io_module`
40			`gpio`
41
42
43
44			`slave_clk`
45	102	jt_eaton
46
47	99	jt_eaton
48
49
50			`clk`
51			`clk`
52
53
54
55
56
57			`slave_reset`
58	102	jt_eaton
59
60	99	jt_eaton
61
62
63			`reset`
64			`reset`
65
66
67
68
69
70
71
72
73
74	120	jt_eaton	`gen_verilog`
75	99	jt_eaton	`104.0`
76			`none`
77	120	jt_eaton	`common`
78			`./tools/verilog/gen_verilog`
79	99	jt_eaton
80
81			`destination`
82			`top.gpio`
83
84
85			`dest_dir`
86	118	jt_eaton	`../verilog`
87	99	jt_eaton
88
89
90
91
92
93	120	jt_eaton	`gen_verilogLib_sim`
94	99	jt_eaton	`105.0`
95			`none`
96	120	jt_eaton	`sim`
97	119	jt_eaton	`./tools/verilog/gen_verilogLib`
98	99	jt_eaton
99
100			`dest_dir`
101	118	jt_eaton	`../views`
102	99	jt_eaton
103
104
105
106	120	jt_eaton
107	125	jt_eaton
108	99	jt_eaton
109
110
111
112
113
114	120	jt_eaton	`fs-common`
115	99	jt_eaton
116	120	jt_eaton
117	99	jt_eaton
118
119	120	jt_eaton	`../verilog/top.gpio.rtl`
120			`verilogSourcefragment`
121	119	jt_eaton
122
123	120	jt_eaton
124
125
126
127			`fs-sim`
128
129	119	jt_eaton
130
131	120	jt_eaton	`../verilog/copyright.v`
132			`verilogSourceinclude`
133	99	jt_eaton
134
135
136
137	120	jt_eaton	`../verilog/common/top.gpio`
138			`verilogSourcemodule`
139	99	jt_eaton
140
141
142	121	jt_eaton	`dest_dir../views/sim/`
143	120	jt_eaton	`verilogSourcelibraryDir`
144	99	jt_eaton
145
146
147
148	120	jt_eaton
149	99	jt_eaton
150			`fs-syn`
151
152	119	jt_eaton
153	99	jt_eaton
154	125	jt_eaton	`dest_dir../views/sim/`
155	120	jt_eaton	`verilogSourcelibraryDir`
156	99	jt_eaton
157
158
159
160
161
162
163	124	jt_eaton
164
165			`fs-lint`
166
167	125	jt_eaton	`dest_dir../views/sim/`
168	124	jt_eaton	`verilogSourcelibraryDir`
169
170
171
172
173
174
175
176
177	99	jt_eaton
178
179
180
181
182
183
184
185
186
187	107	jt_eaton	`Hierarchical`
188
189
190			`spirit:library="io"`
191			`spirit:name="io_module"`
192			`spirit:version="gpio.designCfg"/>`
193
194
195
196	127	jt_eaton	`common:socgen.opencores.org:`
197	120	jt_eaton	`::`
198			`Verilog`
199
200
201			`fs-common`
202
203
204
205
206	127	jt_eaton	`sim:socgen.opencores.org:`
207	99	jt_eaton	`::`
208			`Verilog`
209
210
211			`fs-sim`
212
213
214
215
216
217
218
219
220
221	119	jt_eaton	`UART_PRESCALE5'b01100`
222			`UART_PRE_SIZE5`
223			`UART_DIV0`
224			`BASE_WIDTH8`
225			`ADDR_WIDTH16`
226			`NMI_MODE8'h00`
227			`IRQ_MODE8'h00`
228	102	jt_eaton
229	99	jt_eaton
230
231	102	jt_eaton
232
233
234
235	99	jt_eaton
236
237
238
239	102	jt_eaton	`enable`
240	99	jt_eaton	`wire`
241	102	jt_eaton	`in`
242	99	jt_eaton
243
244
245
246
247	102	jt_eaton	`wait_n`
248	99	jt_eaton	`wire`
249	102	jt_eaton	`out`
250	99	jt_eaton
251
252
253	102	jt_eaton	`gpio_0_out`
254	99	jt_eaton	`wire`
255	102	jt_eaton	`out`
256	99	jt_eaton	`70`
257
258
259	102	jt_eaton	`gpio_0_oe`
260	99	jt_eaton	`wire`
261	102	jt_eaton	`out`
262	99	jt_eaton	`70`
263
264
265
266	102	jt_eaton	`gpio_0_in`
267	99	jt_eaton	`wire`
268	102	jt_eaton	`in`
269	99	jt_eaton	`70`
270
271
272	102	jt_eaton	`gpio_1_out`
273	99	jt_eaton	`wire`
274	102	jt_eaton	`out`
275	99	jt_eaton	`70`
276
277
278	102	jt_eaton	`gpio_1_oe`
279	99	jt_eaton	`wire`
280	102	jt_eaton	`out`
281	99	jt_eaton	`70`
282
283
284
285
286	102	jt_eaton	`gpio_1_in`
287	99	jt_eaton	`wire`
288	102	jt_eaton	`in`
289	99	jt_eaton	`70`
290
291
292	102	jt_eaton	`timer_irq`
293	99	jt_eaton	`wire`
294	102	jt_eaton	`out`
295	99	jt_eaton	`10`
296
297
298	102	jt_eaton	`pic_irq`
299	99	jt_eaton	`wire`
300	102	jt_eaton	`out`
301	99	jt_eaton
302
303	102	jt_eaton	`pic_nmi`
304	99	jt_eaton	`wire`
305	102	jt_eaton	`out`
306	99	jt_eaton
307
308	102	jt_eaton	`pic_irq_in`
309	99	jt_eaton	`wire`
310	102	jt_eaton	`in`
311	99	jt_eaton	`70`
312
313
314
315	102	jt_eaton	`cts_pad_in`
316	99	jt_eaton	`wire`
317	102	jt_eaton	`in`
318	99	jt_eaton
319
320	102	jt_eaton	`rts_pad_out`
321	99	jt_eaton	`wire`
322	102	jt_eaton	`out`
323	99	jt_eaton
324
325	102	jt_eaton	`rx_irq`
326	99	jt_eaton	`wire`
327	102	jt_eaton	`out`
328	99	jt_eaton
329
330	102	jt_eaton	`tx_irq`
331	99	jt_eaton	`wire`
332	102	jt_eaton	`out`
333	99	jt_eaton
334
335
336
337
338
339
340
341
342
343
344
345
346
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[/] [socgen/] [trunk/] [projects/] [opencores.org/] [io/] [ip/] [io_module/] [rtl/] [xml/] [io_module_gpio.xml] - Blame information for rev 127