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[/] [socgen/] [trunk/] [projects/] [opencores.org/] [or1k/] [ip/] [or1200/] [rtl/] [xml/] [or1200_dbg.xml] - Blame information for rev 117

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
or1k
or1200
dbg
 
 

 
 
 clk
  
  
  
    
      
        clk
        clk_i
      
    
 
 
 
 reset
  
  
  
    
      
        reset
        rst_i
      
    
 
 
 
 
 
 
iwb
   
   
   
     
 
        
         adr
         
         iwb_adr
           310
         
       
 
 
        
         wdata
         
         iwb_wdata
           310
         
       
 
 
        
         rdata
         
         iwb_rdata
           310
         
       
 
 
        
         sel
         
         iwb_sel
           30
         
       
 
 
 
        
         ack
         
         iwb_ack
         
       
 
 
        
         cyc
         
         iwb_cyc
         
       
 
 
 
        
         stb
         
         iwb_stb
         
       
 
 
        
         we
         
         iwb_we
         
       
 
 
        
         err
         
         iwb_err
         
       
 
       
         rty
         
         iwb_rty
         
       
 
 
        
         cti
         
         iwb_cti
           20
         
       
 
 
        
         bte
         
         iwb_bte
           10
         
       
 
 
 
 
 
     
 

 
 
 
 
 
dwb
   
   
   
     
 
        
         adr
         
         dwb_adr
           310
         
       
 
 
        
         wdata
         
         dwb_wdata
           310
         
       
 
 
        
         rdata
         
         dwb_rdata
           310
         
       
 
 
        
         sel
         
         dwb_sel
           30
         
       
 
 
 
        
         ack
         
         dwb_ack
         
       
 
 
        
         cyc
         
         dwb_cyc
         
       
 
 
 
        
         stb
         
         dwb_stb
         
       
 
 
        
         we
         
         dwb_we
         
       
 
 
        
         err
         
         dwb_err
         
       
 
 
        
         rty
         
         dwb_rty
         
       
 
 
        
         cti
         
         dwb_cti
           20
         
       
 
 
        
         bte
         
         dwb_bte
           10
         
       
 
 
 
     
 

 
 
 
 
 
 
 dbg
  
  
  
    
 
        
         addr
         
         dbg_addr
           310
         
       
 
 
        
         wdata
         
         dbg_wdata
           310
         
       
 
 
        
         rdata
         
         dbg_rdata
           310
         
       
 
 
        
         lss
         
         dbg_lss
           30
         
       
 
 
        
         is
         
         dbg_is
           10
         
       
 
 
        
         wp
         
         dbg_wp
           100
         
       
 
 
 
 
      
        stall
        dbg_stall
      
 
 
      
        ewt
        dbg_ewt
      
 
 
      
        bp
        dbg_bp
      
 
 
      
        stb
        dbg_stb
      
 
 
      
        we
        dbg_we
      
 
 
      
        ack
        dbg_ack
      
 
 
    
 
 
 
 
 
 
 

 
 
 
 
 
 

 

  header_maker
  102.0
  none
  headers
  gen_header
    
    
      inst_path
      cpu.spr_mux.spr_bus
    
    
      dest_dir
      ../../sw/
    
  

 
 
 
 

  verilog_maker
  104.0
  none
  gen_verilog
    
    
      destination
      top.dbg
    
    
      dest_dir
      ../verilog/
    
  

 
 
 
 

  leaf_maker
  105.0
  none
  gen_verilogLib
    
    
      dest_dir
      ../views/
    
  

 

 
 

 
 
 
   
      fs-sim
 
      
        
        ../verilog/or1200_defines.v
        verilogInclude
      
 
      
        
        ../verilog/or1200_monitor_defines.v
        verilogInclude
      
 
      
        
        ../verilog/sim/top.dbg
        verilogSource
      
 
      
        
        ../verilog/or1200_dpram_256x32.v
        verilogSource
      
 
 
 
 
      
        
        ../verilog/or1200_tpram_32x32.v
        verilogSource
      
 
 
      
        
        ../verilog/or1200_dpram.v
        verilogSource
      
 
 
 
 
 
 
 
 
 
      
        
        ../verilog/or1200_spram_32_bw.v
        verilogSource
      
 
 
 
 
 
 
 
 
 
 
 
 
      
        
        ../verilog/or1200_spram.v
        verilogSource
      
 
 
      
        
        ../verilog/or1200_monitor.v
        verilogSource
      
 
      
        
        ../verilog/wb_checker.v
        verilogSource
      
 
 
      
        
        ../verilog/top.or1200_mon
        verilogFragment
      
 
 
 
      
        
        ../verilog/top.dbg
        verilogFragment
      
 
 
 
      
        ../views/sim/
        verilogLibraryDir
      
 
   
 
   
      fs-syn
 
      
        
        ../verilog/or1200_defines.v
        verilogInclude
      
 
      
        
        ../verilog/synthesys
        verilogInclude
      
 
 
 
 
 
      
        
        ../verilog/syn/top.dbg
        verilogSource
      
 
 
 
 
 
 
 
 
      
        
        ../verilog/or1200_dpram_256x32.v
        verilogSource
      
 
 
 
 
 
      
        
        ../verilog/or1200_tpram_32x32.v
        verilogSource
      
 
 
      
        
        ../verilog/or1200_dpram.v
        verilogSource
      
 
 
 
      
        
        ../verilog/or1200_spram_32_bw.v
        verilogSource
      
 
 
 
      
        
        ../verilog/or1200_spram.v
        verilogSource
      
 
      
        
        ../verilog/top.dbg
        verilogFragment
      
 
      
        ../views/syn/
        verilogLibraryDir
      
 
 
   
 
 
 
 
 
  
 
 
 
 
 

       
 
              
              Hierarchical
              
              
                                   spirit:library="or1k"
                                   spirit:name="or1200"
                                   spirit:version="dbg.designCfg"/>
              
 
 
              
              headers
              ::
              Verilog
              
              
 
 
 
              
              sim
              ::
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn
              ::
              Verilog
              
                     
                            fs-syn
                     
              
 
      
 
 
 
 
 
 

 
dw
`OR1200_OPERAND_WIDTH
 
aw
`OR1200_OPERAND_WIDTH
 
ppic_ints
`OR1200_PIC_INTS
 
iwb_bl
`OR1200_IWB_BL
 
dwb_bl
`OR1200_DWB_BL
 
alt_boot_adr
`OR1200_BOOT_ADR
 
boot_adr
alt_boot_adr
 
qmem_num_decode
12
 
qmem_inst_addr
12'h008
 
qmem_data_addr
12'h008
 
qmem_adr_width
12
 
qmem_mem_size
16384
 
qmem_SRAM_MEM_FILE
"NONE"
 
immu_cache_en
3
 
dmmu_cache_en
3
 
 
 
 

 
 

 
 
 
 

pic_ints_i
wire
inppic_ints-10

 
 

sig_tick
wire
out

 
 
 

pm_cpustall_i
wire
in

 
 
 
 

pm_clksd_o
wire
out30

 
 
 

pm_dc_gate_o
wire
out

 
 

pm_ic_gate_o
wire
out

 
 
 

pm_dmmu_gate_o
wire
out

 

pm_immu_gate_o
wire
out

 
 
 

pm_tt_gate_o
wire
out

 
 

pm_cpu_gate_o
wire
out

 
 

pm_wakeup_o
wire
out

 
 

pm_lvolt_o
wire
out

 
 
 

 
 
 
 
 
 
 
 
 

 
 
 
 

 

dw`OR1200_OPERAND_WIDTH

 

aw`OR1200_OPERAND_WIDTH

 

ppic_ints`OR1200_PIC_INTS

 

iwb_bl`OR1200_IWB_BL

 

dwb_bl`OR1200_DWB_BL

 

alt_boot_adr`OR1200_BOOT_ADR

 

boot_adralt_boot_adr

 

qmem_num_decode12

 

qmem_inst_addr12'h008

 

qmem_data_addr12'h008

 

qmem_adr_width12

 

qmem_mem_size16384

 

qmem_SRAM_MEM_FILE"NONE"

 

immu_cache_en3

 

dmmu_cache_en3

 
 
 
 

 
 
 
 
 


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Subversion Repositories socgen

[/] [socgen/] [trunk/] [projects/] [opencores.org/] [or1k/] [ip/] [or1200/] [rtl/] [xml/] [or1200_dbg.xml] - Blame information for rev 117

Line No.	Rev	Author	Line
1	101	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
33			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
34			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
35
36			`opencores.org`
37			`or1k`
38			`or1200`
39			`dbg`
40
41
42
43
44
45			`clk`
46
47
48
49
50
51			`clk`
52			`clk_i`
53
54
55
56
57
58			`reset`
59
60
61
62
63
64			`reset`
65			`rst_i`
66
67
68
69
70
71
72
73
74			`iwb`
75
76
77
78
79
80
81			`adr`
82
83	116	jt_eaton	`iwb_adr`
84	103	jt_eaton	`310`
85	101	jt_eaton
86
87
88
89
90			`wdata`
91
92	116	jt_eaton	`iwb_wdata`
93	103	jt_eaton	`310`
94	101	jt_eaton
95
96
97
98
99			`rdata`
100
101	116	jt_eaton	`iwb_rdata`
102	103	jt_eaton	`310`
103	101	jt_eaton
104
105
106
107
108			`sel`
109
110	116	jt_eaton	`iwb_sel`
111	101	jt_eaton	`30`
112
113
114
115
116
117
118			`ack`
119
120	116	jt_eaton	`iwb_ack`
121	101	jt_eaton
122
123
124
125
126			`cyc`
127
128	116	jt_eaton	`iwb_cyc`
129	101	jt_eaton
130
131
132
133
134
135			`stb`
136
137	116	jt_eaton	`iwb_stb`
138	101	jt_eaton
139
140
141
142
143			`we`
144
145	116	jt_eaton	`iwb_we`
146	101	jt_eaton
147
148
149
150
151			`err`
152
153	116	jt_eaton	`iwb_err`
154	101	jt_eaton
155
156
157	113	jt_eaton
158	101	jt_eaton	`rty`
159
160	116	jt_eaton	`iwb_rty`
161	101	jt_eaton
162
163
164
165	113	jt_eaton
166			`cti`
167
168	116	jt_eaton	`iwb_cti`
169	113	jt_eaton	`20`
170
171
172
173
174
175			`bte`
176
177	116	jt_eaton	`iwb_bte`
178	113	jt_eaton	`10`
179
180
181
182
183
184
185
186	101	jt_eaton
187
188
189
190
191
192
193
194			`dwb`
195
196
197
198
199
200
201			`adr`
202
203	116	jt_eaton	`dwb_adr`
204	103	jt_eaton	`310`
205	101	jt_eaton
206
207
208
209
210			`wdata`
211
212	116	jt_eaton	`dwb_wdata`
213	103	jt_eaton	`310`
214	101	jt_eaton
215
216
217
218
219			`rdata`
220
221	116	jt_eaton	`dwb_rdata`
222	103	jt_eaton	`310`
223	101	jt_eaton
224
225
226
227
228			`sel`
229
230	116	jt_eaton	`dwb_sel`
231	101	jt_eaton	`30`
232
233
234
235
236
237
238			`ack`
239
240	116	jt_eaton	`dwb_ack`
241	101	jt_eaton
242
243
244
245
246			`cyc`
247
248	116	jt_eaton	`dwb_cyc`
249	101	jt_eaton
250
251
252
253
254
255			`stb`
256
257	116	jt_eaton	`dwb_stb`
258	101	jt_eaton
259
260
261
262
263			`we`
264
265	116	jt_eaton	`dwb_we`
266	101	jt_eaton
267
268
269
270
271			`err`
272
273	116	jt_eaton	`dwb_err`
274	101	jt_eaton
275
276
277
278
279			`rty`
280
281	116	jt_eaton	`dwb_rty`
282	101	jt_eaton
283
284
285
286	113	jt_eaton
287			`cti`
288
289	116	jt_eaton	`dwb_cti`
290	113	jt_eaton	`20`
291
292
293
294
295
296			`bte`
297
298	116	jt_eaton	`dwb_bte`
299	113	jt_eaton	`10`
300
301
302
303
304
305	101	jt_eaton
306
307
308
309
310
311
312
313
314	113	jt_eaton	`dbg`
315
316
317
318
319	101	jt_eaton
320	113	jt_eaton
321			`addr`
322
323	116	jt_eaton	`dbg_addr`
324	113	jt_eaton	`310`
325
326
327
328
329
330			`wdata`
331
332	116	jt_eaton	`dbg_wdata`
333	113	jt_eaton	`310`
334
335
336
337
338
339			`rdata`
340
341	116	jt_eaton	`dbg_rdata`
342	113	jt_eaton	`310`
343
344
345
346
347
348			`lss`
349
350	116	jt_eaton	`dbg_lss`
351	113	jt_eaton	`30`
352
353
354
355
356
357			`is`
358
359	116	jt_eaton	`dbg_is`
360	113	jt_eaton	`10`
361
362
363
364
365
366			`wp`
367
368	116	jt_eaton	`dbg_wp`
369	113	jt_eaton	`100`
370
371
372
373
374
375
376
377			`stall`
378	116	jt_eaton	`dbg_stall`
379	113	jt_eaton
380
381
382
383			`ewt`
384	116	jt_eaton	`dbg_ewt`
385	113	jt_eaton
386
387
388
389			`bp`
390	116	jt_eaton	`dbg_bp`
391	113	jt_eaton
392
393
394
395			`stb`
396	116	jt_eaton	`dbg_stb`
397	113	jt_eaton
398
399
400
401			`we`
402	116	jt_eaton	`dbg_we`
403	113	jt_eaton
404
405
406
407			`ack`
408	116	jt_eaton	`dbg_ack`
409	113	jt_eaton
410
411
412
413
414
415
416
417
418
419
420	101	jt_eaton
421
422
423
424
425
426
427
428
429	116	jt_eaton
430			`header_maker`
431			`102.0`
432			`none`
433			`headers`
434	117	jt_eaton	`gen_header`
435	116	jt_eaton
436
437			`inst_path`
438			`cpu.spr_mux.spr_bus`
439
440
441			`dest_dir`
442			`../../sw/`
443
444
445
446	101	jt_eaton
447	116	jt_eaton
448
449
450	101	jt_eaton
451			`verilog_maker`
452			`104.0`
453			`none`
454	117	jt_eaton	`gen_verilog`
455	101	jt_eaton
456
457			`destination`
458			`top.dbg`
459
460
461			`dest_dir`
462			`../verilog/`
463
464
465
466
467
468
469
470
471			`leaf_maker`
472			`105.0`
473			`none`
474	117	jt_eaton	`gen_verilogLib`
475	101	jt_eaton
476
477			`dest_dir`
478			`../views/`
479
480
481
482
483
484
485
486
487
488
489
490
491			`fs-sim`
492
493
494
495	113	jt_eaton	`../verilog/or1200_defines.v`
496	101	jt_eaton	`verilogInclude`
497
498
499	113	jt_eaton
500
501			`../verilog/or1200_monitor_defines.v`
502			`verilogInclude`
503
504	101	jt_eaton
505	113	jt_eaton
506
507			`../verilog/sim/top.dbg`
508			`verilogSource`
509
510	101	jt_eaton
511	113	jt_eaton
512
513			`../verilog/or1200_dpram_256x32.v`
514			`verilogSource`
515
516	101	jt_eaton
517
518	113	jt_eaton
519
520	101	jt_eaton
521
522	113	jt_eaton	`../verilog/or1200_tpram_32x32.v`
523	101	jt_eaton	`verilogSource`
524
525
526
527	113	jt_eaton
528
529			`../verilog/or1200_dpram.v`
530			`verilogSource`
531
532	101	jt_eaton
533
534	113	jt_eaton
535
536
537
538
539
540	114	jt_eaton
541	101	jt_eaton
542
543	113	jt_eaton	`../verilog/or1200_spram_32_bw.v`
544			`verilogSource`
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560			`../verilog/or1200_spram.v`
561			`verilogSource`
562
563
564
565
566
567			`../verilog/or1200_monitor.v`
568			`verilogSource`
569
570
571
572
573			`../verilog/wb_checker.v`
574			`verilogSource`
575
576
577
578
579
580			`../verilog/top.or1200_mon`
581	101	jt_eaton	`verilogFragment`
582
583
584
585
586
587	113	jt_eaton
588	114	jt_eaton	`../verilog/top.dbg`
589	113	jt_eaton	`verilogFragment`
590
591
592
593
594
595	101	jt_eaton	`../views/sim/`
596			`verilogLibraryDir`
597
598
599
600
601
602			`fs-syn`
603
604
605
606	113	jt_eaton	`../verilog/or1200_defines.v`
607	101	jt_eaton	`verilogInclude`
608
609
610	113	jt_eaton
611
612			`../verilog/synthesys`
613			`verilogInclude`
614
615	101	jt_eaton
616
617	113	jt_eaton
618
619
620	101	jt_eaton
621
622			`../verilog/syn/top.dbg`
623			`verilogSource`
624
625
626
627	113	jt_eaton
628
629
630
631
632	114	jt_eaton
633	101	jt_eaton
634
635	113	jt_eaton	`../verilog/or1200_dpram_256x32.v`
636			`verilogSource`
637	101	jt_eaton
638
639
640
641
642	113	jt_eaton
643	101	jt_eaton
644	113	jt_eaton
645			`../verilog/or1200_tpram_32x32.v`
646			`verilogSource`
647
648
649
650
651
652			`../verilog/or1200_dpram.v`
653			`verilogSource`
654
655
656
657
658
659
660			`../verilog/or1200_spram_32_bw.v`
661			`verilogSource`
662
663
664
665
666
667
668			`../verilog/or1200_spram.v`
669			`verilogSource`
670
671
672
673
674	114	jt_eaton	`../verilog/top.dbg`
675	113	jt_eaton	`verilogFragment`
676
677
678
679	101	jt_eaton	`../views/syn/`
680			`verilogLibraryDir`
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699	107	jt_eaton
700			`Hierarchical`
701
702
703			`spirit:library="or1k"`
704			`spirit:name="or1200"`
705			`spirit:version="dbg.designCfg"/>`
706
707	101	jt_eaton
708
709	116	jt_eaton
710			`headers`
711			`::`
712			`Verilog`
713
714
715	101	jt_eaton
716	116	jt_eaton
717
718	101	jt_eaton
719			`sim`
720			`::`
721			`Verilog`
722
723
724			`fs-sim`
725
726
727
728
729
730			`syn`
731			`::`
732			`Verilog`
733
734
735			`fs-syn`
736
737
738
739
740
741
742
743
744
745
746
747	113	jt_eaton
748	116	jt_eaton	`dw`
749			`OR1200_OPERAND_WIDTH
750	113	jt_eaton
751	116	jt_eaton	`aw`
752			`OR1200_OPERAND_WIDTH
753
754			`ppic_ints`
755			`OR1200_PIC_INTS
756
757			`iwb_bl`
758			`OR1200_IWB_BL
759
760			`dwb_bl`
761			`OR1200_DWB_BL
762
763			`alt_boot_adr`
764			`OR1200_BOOT_ADR
765
766			`boot_adr`
767			`alt_boot_adr`
768	114	jt_eaton
769	116	jt_eaton	`qmem_num_decode`
770			`12`
771
772			`qmem_inst_addr`
773			`12'h008`
774
775			`qmem_data_addr`
776			`12'h008`
777
778			`qmem_adr_width`
779			`12`
780
781			`qmem_mem_size`
782			`16384`
783
784			`qmem_SRAM_MEM_FILE`
785			`"NONE"`
786
787			`immu_cache_en`
788			`3`
789
790			`dmmu_cache_en`
791			`3`
792
793
794
795
796	101	jt_eaton
797
798
799
800
801
802
803
804
805			`pic_ints_i`
806			`wire`
807			`inppic_ints-10`
808
809
810
811	107	jt_eaton
812			`sig_tick`
813			`wire`
814			`out`
815
816	101	jt_eaton
817
818	107	jt_eaton
819	101	jt_eaton
820			`pm_cpustall_i`
821			`wire`
822			`in`
823
824
825
826
827
828
829			`pm_clksd_o`
830			`wire`
831			`out30`
832
833
834
835
836
837			`pm_dc_gate_o`
838			`wire`
839			`out`
840
841
842
843
844			`pm_ic_gate_o`
845			`wire`
846			`out`
847
848
849
850
851
852			`pm_dmmu_gate_o`
853			`wire`
854			`out`
855
856
857
858			`pm_immu_gate_o`
859			`wire`
860			`out`
861
862
863
864
865
866			`pm_tt_gate_o`
867			`wire`
868			`out`
869
870
871
872
873			`pm_cpu_gate_o`
874			`wire`
875			`out`
876
877
878
879
880			`pm_wakeup_o`
881			`wire`
882			`out`
883
884
885
886
887			`pm_lvolt_o`
888			`wire`
889			`out`
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909	116	jt_eaton
910	101	jt_eaton
911	116	jt_eaton
912			dw`OR1200_OPERAND_WIDTH
913
914	101	jt_eaton
915	116	jt_eaton
916			aw`OR1200_OPERAND_WIDTH
917
918
919
920			ppic_ints`OR1200_PIC_INTS
921
922
923
924			iwb_bl`OR1200_IWB_BL
925
926
927
928			dwb_bl`OR1200_DWB_BL
929
930
931
932			alt_boot_adr`OR1200_BOOT_ADR
933
934
935
936			`boot_adralt_boot_adr`
937
938	101	jt_eaton
939	116	jt_eaton
940			`qmem_num_decode12`
941
942	101	jt_eaton
943	116	jt_eaton
944			`qmem_inst_addr12'h008`
945
946	101	jt_eaton
947	116	jt_eaton
948			`qmem_data_addr12'h008`
949
950	101	jt_eaton
951	116	jt_eaton
952			`qmem_adr_width12`
953
954
955
956			`qmem_mem_size16384`
957
958
959
960			`qmem_SRAM_MEM_FILE"NONE"`
961
962
963
964			`immu_cache_en3`
965
966
967
968			`dmmu_cache_en3`
969
970
971
972
973
974
975
976
977
978
979
980	101	jt_eaton