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//
// TT Mode Register bits (or no register)
//

wire    [31:0]  ttmr;   // TTMR bits

//
// TT Count Register bits (or no register)
//

wire    [31:0]  ttcr;   // TTCR bits
//
// Internal wires & regs
//
wire            ttmr_sel;       // TTMR select
wire            ttcr_sel;       // TTCR select
wire            match;          // Asserted when TTMR[TP]
                                // is equal to TTCR[27:0]
wire            restart;        // Restart counter when asserted
wire            stop;           // Stop counter when asserted

reg [31:0] next_ttmr;
reg [31:0] next_ttcr;





always @(*)
        begin
        next_ttmr                             = ttmr;
        if (ttmr[`OR1200_TT_TTMR_IE])
                next_ttmr[`OR1200_TT_TTMR_IP] =  ttmr[`OR1200_TT_TTMR_IP] | (match & ttmr[`OR1200_TT_TTMR_IE]);

        end


//
// Write to or increment of TTCR
//



always @(*)
        if (restart)            next_ttcr =  32'b0;
        else 
        if (!stop)              next_ttcr =  ttcr + 32'd1;
        else                    next_ttcr =  ttcr;



//
// A match when TTMR[TP] is equal to TTCR[27:0]
//
assign match = (ttmr[`OR1200_TT_TTMR_TP] == ttcr[27:0]) ? 1'b1 : 1'b0;

//
// Restart when match and TTMR[M]==0x1
//
assign restart = match && (ttmr[`OR1200_TT_TTMR_M] == 2'b01);

//
// Stop when match and TTMR[M]==0x2 or when TTMR[M]==0x0 or when RISC is stalled by debug unit
//
assign stop = match & (ttmr[`OR1200_TT_TTMR_M] == 2'b10) | (ttmr[`OR1200_TT_TTMR_M] == 2'b00) | du_stall;

//
// Generate an interrupt request
//
assign intr = ttmr[`OR1200_TT_TTMR_IP];




 `VARIANT`SPR_REG
#(  .UNSELECTED ({32{1'b0}}),
    .UNMAPPED   ({32{1'b0}}),
    .TTMR_RST   ( 32'b0),
    .TTCR_RST   ( 32'b0))
spr_reg
 (
                          .clk        ( clk       ),
                          .reset      ( rst       ),
                          .enable     (1'b1       ),
                          .cs         ( spr_cs    ),
                          .wr         ( spr_write ),
                          .rd         (1'b1       ),
                          .wdata      ( spr_dat_i ),
                          .rdata      ( spr_dat_o ),
                          .byte_lanes (1'b1       ),
                          .addr       ( spr_addr  ),
                          .ttmr       ( ttmr      ),
                          .next_ttmr  ( next_ttmr ),
                          .ttmr_rdata ( ttmr      ),
                          .ttmr_dec   ( ttmr_sel  ),
                          .ttmr_wr_0  (           ),
                          .ttmr_cs    (           ),
                          .ttcr       ( ttcr      ),
                          .next_ttcr  ( next_ttcr ),
                          .ttcr_rdata ( ttcr      ),
                          .ttcr_dec   ( ttcr_sel  ),
                          .ttcr_wr_0  (           ), 
                          .ttcr_cs    (           )
);