OpenCores
URL https://opencores.org/ocsvn/pdp1/pdp1/trunk

Subversion Repositories pdp1

[/] [pdp1/] - Rev 18

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
18 Minor adjustments

Timestamp after receiving data, removed unnecessary closure,
derive Debug for Vertex struct.		 yannv 2559d 02h /pdp1/
17 Very hacky code to read paper tape files.

Isim reads integers as 32-bit signed little endian,
so we split that into the constituent bytes.

Simulation has now managed to use our preloaded
readin program to read the RIM of same program,
which contains another type of loader (with
checksumming), which read the program in again.
That's a lot of work for no real progress, but
the computer loads code.

To do: hardwired logic read in mode, tool to
feed RIM files to hardware, possibly a way to
load new tapes in simulation.		 yannv 2560d 01h /pdp1/
16 Test data input for oscilloscope. Draws a circle. yannv 2560d 06h /pdp1/
15 Rust oscilloscope: thread for async input yannv 2560d 06h /pdp1/
14 Streaming data input in Rust oscilloscope.

Next up: Non-blocking input.		 yannv 2560d 07h /pdp1/
13 Proof of concept Rust+Glium XY oscilloscope code.

To do: add input capability and proper time keeping.		 yannv 2561d 03h /pdp1/
12 Proof of concept XY plotting in HTML canvas

Performance on my workstation is just about fast enough.
Work on a means of feeding points in.		 yannv 2561d 08h /pdp1/
11 Rough xy oscilloscope display program.

Not actually usable, way too slow.		 yannv 2562d 23h /pdp1/
10 testtop: use a uart to send serial data yannv 2563d 02h /pdp1/
9 Avoid unsigned port for PC. yannv 2563d 02h /pdp1/
8 Avoid inout signal. yannv 2563d 02h /pdp1/
7 Typo fix. yannv 2563d 02h /pdp1/
6 Modified to use dual-port RAM for scanline buffers, instead of one RAM per scanline.
Note that XST fails to create dual-port RAM if write data on one port is constant!
Next step is to use generic_dpram from opencores common.		 yannv 4791d 06h /pdp1/
5 Add _i and _o suffixes to ports. yannv 4791d 07h /pdp1/
4 Filled in some comments in vector2scanline.v.
My very first Verilog module, bear with me.		 yannv 4804d 02h /pdp1/
3 Unpacked source code for further development in svn. yannv 4804d 02h /pdp1/
2 Added Mercurial bundle of pre-subversion source code. yannv 4804d 02h /pdp1/
1 The project and the structure was created root 4805d 03h /pdp1/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.