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[/] [socgen/] [trunk/] [projects/] [opencores.org/] [or1k/] - Rev 127

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Rev Log message Author Age Path
127 final cleanup before DAC jt_eaton 28m /socgen/trunk/projects/opencores.org/or1k/
126 added mor1kx
cleanup		 jt_eaton 53d 05h /socgen/trunk/projects/opencores.org/or1k/
125 Added two new 6502 cores in www.6502.org

cleaned up sogen xml files and added module name control		 jt_eaton 97d 23h /socgen/trunk/projects/opencores.org/or1k/
124 beta release candidate 1
changed design.xml name
aligned schema with filesystem		 jt_eaton 151d 02h /socgen/trunk/projects/opencores.org/or1k/
122 Moved Nexys2 from opencores.org to digilentinc.com
Moved jtag_rpc and or1k Busdefs into cde_jtag and or1200 components		 jt_eaton 173d 21h /socgen/trunk/projects/opencores.org/or1k/
121 cleaned up sims, added autogenerated test bench files
removed mrisc and experimental or1k code		 jt_eaton 194d 03h /socgen/trunk/projects/opencores.org/or1k/
120 clean up componentGenerators names and directories
sim + lint now synthesis TestBench		 jt_eaton 212d 03h /socgen/trunk/projects/opencores.org/or1k/
119 moved copyright files into /verilog
changed cde copyright to apache from gplv3
split out tools into separate subdirectories
changed design.xml files to socgen: namespace		 jt_eaton 246d 22h /socgen/trunk/projects/opencores.org/or1k/
118 optimized gen_verilog
added padring support
added configuration support
added jtag sims
added accellera candidate bus defs		 jt_eaton 282d 07h /socgen/trunk/projects/opencores.org/or1k/
117 added yellow pages tools jt_eaton 310d 02h /socgen/trunk/projects/opencores.org/or1k/
116 added build_header
now use build_register for all spr components
resynced or1200 code back to use orbuild toolchain		 jt_eaton 344d 23h /socgen/trunk/projects/opencores.org/or1k/
115 split or1200_cpu up into all ip-xact components
removed dead files		 jt_eaton 389d 03h /socgen/trunk/projects/opencores.org/or1k/
114 moved or1200 connectivity out of verilog and into ip-xact
added or1200_boot block
removed force of 00 on lowest iwb_addr bits		 jt_eaton 401d 03h /socgen/trunk/projects/opencores.org/or1k/
113 started refactoring or1200 jt_eaton 406d 19h /socgen/trunk/projects/opencores.org/or1k/
108 removed unneeded files jt_eaton 434d 06h /socgen/trunk/projects/opencores.org/or1k/
107 added designCfg files to all modules jt_eaton 434d 09h /socgen/trunk/projects/opencores.org/or1k/
103 added user guide
resynced to local repository		 jt_eaton 464d 23h /socgen/trunk/projects/opencores.org/or1k/
102 all ip-xact files now readable by kactus2 jt_eaton 526d 19h /socgen/trunk/projects/opencores.org/or1k/
101 Added new designs for minsoc release candidate
convert tool set to parse proper ip-xact

THIS WILL BREAK ALL THE OLD DESIGNS UNTIL I FIX THEIR IP_XACT		 jt_eaton 527d 20h /socgen/trunk/projects/opencores.org/or1k/

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