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Subversion Repositories spi_master_slave

[/] [spi_master_slave/] [trunk/] [syn/] [spi_master_atlys.ucf] - Rev 12

Rev	Log message	Author	Age	Path
12	SPI_SLAVE: v2.00.0110 [JD] FIX: CPHA bugs: -- - redesigned core clocking to address all CPOL and CPHA configurations. -- - added CHANGE_EDGE to the FSM register transfer logic, to have MISO change at opposite -- clock phases from SHIFT_EDGE. -- Removed global signal setting at the FSM, implementing exhaustive explicit signal attributions -- for each state, to avoid reported inference problems in some synthesis engines. -- Streamlined port names and indentation blocks.	jdoin	663d 08h	/spi_master_slave/trunk/syn/spi_master_atlys.ucf
10	v1.11.0080: Changed sampling of MISO in spi_master.vhd (removed the input register). Verified master+slave cores in silicon on a Spartan-6 FPGA at 100MHz, using Xilinx ISE 13.1 and a Digilent Atlys board. Project is included in trunk/syn/spi_master_atlys.xise.	jdoin	675d 08h	/spi_master_slave/trunk/syn/spi_master_atlys.ucf
5	Changed clocking to use a single high-speed clock for the whole core, using clock enables to control slower timing. Added SPI line clock divider from high-speed system clock. Added pipeline delay logic to sync phase of SCK and MOSI, enabling very high operating frequencies. Verified in silicon for SCK and MOSI at 50MHz, with very robust operation.	jdoin	681d 07h	/spi_master_slave/trunk/syn/spi_master_atlys.ucf