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pci
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http://opencores.org/websvn,listing?repname=pci&path=%2Fpci%2Ftrunk%2F&
Sat, 18 May 2013 12:32:34 +0100
FeedCreator 1.7.2
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New directory structure.
http://opencores.org/websvn,revision?repname=pci&path=%2Fpci%2Ftrunk%2F&rev=154
<div><strong>Rev 154 - root</strong> (8 file(s) modified)</div><div>New directory structure.</div>- /branches<br />+ /pci<br />+ /pci/branches<br />+ /pci/tags<br />+ /pci/trunk<br />+ /pci/web_uploads<br />- /tags<br />- /trunk<br />
root
Tue, 10 Mar 2009 08:24:20 +0100
http://opencores.org/websvn,revision?repname=pci&path=%2Fpci%2Ftrunk%2F&rev=154
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Write burst performance patch applied.
Not tested. Everything should be backwards
compatible, ...
http://opencores.org/websvn,revision?repname=pci&path=%2Ftrunk%2F&rev=153
<div><strong>Rev 153 - mihad</strong> (4 file(s) modified)</div><div>Write burst performance patch applied.<br />
Not tested. Everything should be backwards<br />
compatible, ...</div>~ /trunk/rtl/verilog/pci_wbw_fifo_control.v<br />~ /trunk/rtl/verilog/pci_wbw_wbr_fifos.v<br />~ /trunk/rtl/verilog/pci_wb_slave.v<br />~ /trunk/rtl/verilog/pci_wb_slave_unit.v<br />
mihad
Tue, 04 Jul 2006 13:16:19 +0100
http://opencores.org/websvn,revision?repname=pci&path=%2Ftrunk%2F&rev=153
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Some regression tests were failing during completion expired testing.
http://opencores.org/websvn,revision?repname=pci&path=%2Ftrunk%2F&rev=152
<div><strong>Rev 152 - mihad</strong> (2 file(s) modified)</div><div>Some regression tests were failing during completion expired testing.</div>~ /trunk/bench/verilog/system.v<br />~ /trunk/sim/rtl_sim/bin/ncsim_waves.rc<br />
mihad
Mon, 04 Apr 2005 14:42:33 +0100
http://opencores.org/websvn,revision?repname=pci&path=%2Ftrunk%2F&rev=152
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Top now sends x's to inputs when output is enabled.
http://opencores.org/websvn,revision?repname=pci&path=%2Ftrunk%2F&rev=151
<div><strong>Rev 151 - mihad</strong> (2 file(s) modified)</div><div>Top now sends x's to inputs when output is enabled.</div>~ /trunk/bench/verilog/system.v<br />~ /trunk/bench/verilog/top.v<br />
mihad
Thu, 23 Sep 2004 14:04:26 +0100
http://opencores.org/websvn,revision?repname=pci&path=%2Ftrunk%2F&rev=151
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The control inputs from PCI are now muxed with control ...
http://opencores.org/websvn,revision?repname=pci&path=%2Ftrunk%2F&rev=150
<div><strong>Rev 150 - mihad</strong> (1 file(s) modified)</div><div>The control inputs from PCI are now muxed with control ...</div>~ /trunk/rtl/verilog/pci_bridge32.v<br />
mihad
Thu, 23 Sep 2004 13:48:53 +0100
http://opencores.org/websvn,revision?repname=pci&path=%2Ftrunk%2F&rev=150
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Removed some unused signals.
http://opencores.org/websvn,revision?repname=pci&path=%2Ftrunk%2F&rev=149
<div><strong>Rev 149 - mihad</strong> (1 file(s) modified)</div><div>Removed some unused signals.</div>~ /trunk/rtl/verilog/pci_conf_space.v<br />
mihad
Thu, 19 Aug 2004 16:04:53 +0100
http://opencores.org/websvn,revision?repname=pci&path=%2Ftrunk%2F&rev=149
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Changed minimum pci image size to 256 bytes because
of some ...
http://opencores.org/websvn,revision?repname=pci&path=%2Ftrunk%2F&rev=148
<div><strong>Rev 148 - mihad</strong> (15 file(s) modified)</div><div>Changed minimum pci image size to 256 bytes because<br />
of some ...</div>~ /trunk/bench/verilog/pci_regression_constants.v<br />~ /trunk/bench/verilog/system.v<br />~ /trunk/bench/verilog/wb_slave_behavioral.v<br />~ /trunk/rtl/verilog/pci_bridge32.v<br />~ /trunk/rtl/verilog/pci_conf_space.v<br />~ /trunk/rtl/verilog/pci_pci_tpram.v<br />~ /trunk/rtl/verilog/pci_target32_interface.v<br />~ /trunk/rtl/verilog/pci_target_unit.v<br />~ /trunk/rtl/verilog/pci_user_constants.v<br />~ /trunk/rtl/verilog/pci_wb_tpram.v<br />~ /trunk/sim/rtl_sim/log/ncsim.log<br />~ /trunk/sim/rtl_sim/log/ncvlog.log<br />~ /trunk/sim/rtl_sim/log/pci_tb.log<br />~ /trunk/sim/rtl_sim/run/ncvlog.args<br />~ /trunk/sim/rtl_sim/run/run_pci_sim_regr.scr<br />
mihad
Thu, 19 Aug 2004 15:27:52 +0100
http://opencores.org/websvn,revision?repname=pci&path=%2Ftrunk%2F&rev=148
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Removed unsinthesizable !== comparation.
http://opencores.org/websvn,revision?repname=pci&path=%2Ftrunk%2F&rev=147
<div><strong>Rev 147 - mihad</strong> (1 file(s) modified)</div><div>Removed unsinthesizable !== comparation.</div>~ /trunk/rtl/verilog/pci_wbs_wbb3_2_wbb2.v<br />
mihad
Mon, 16 Aug 2004 09:12:01 +0100
http://opencores.org/websvn,revision?repname=pci&path=%2Ftrunk%2F&rev=147
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Update. Overwrite of previous wrong version upload.
http://opencores.org/websvn,revision?repname=pci&path=%2Ftrunk%2F&rev=146
<div><strong>Rev 146 - mihad</strong> (2 file(s) modified)</div><div>Update. Overwrite of previous wrong version upload.</div>~ /trunk/doc/pci_specification.doc<br />~ /trunk/doc/pci_specification.pdf<br />
mihad
Fri, 16 Jul 2004 15:36:31 +0100
http://opencores.org/websvn,revision?repname=pci&path=%2Ftrunk%2F&rev=146
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PDF regenerated.
http://opencores.org/websvn,revision?repname=pci&path=%2Ftrunk%2F&rev=145
<div><strong>Rev 145 - mihad</strong> (1 file(s) modified)</div><div>PDF regenerated.</div>~ /trunk/doc/pci_specification.pdf<br />
mihad
Fri, 16 Jul 2004 14:45:14 +0100
http://opencores.org/websvn,revision?repname=pci&path=%2Ftrunk%2F&rev=145
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Added PCI Bridge configuration software provided by
Friedrich Ralph.
http://opencores.org/websvn,revision?repname=pci&path=%2Ftrunk%2F&rev=144
<div><strong>Rev 144 - mihad</strong> (4 file(s) modified)</div><div>Added PCI Bridge configuration software provided by<br />
Friedrich Ralph.</div>+ /trunk/sw<br />+ /trunk/sw/configurator<br />+ /trunk/sw/configurator/PCIBridgeConfig.exe<br />+ /trunk/sw/configurator/qtintf.dll<br />
mihad
Fri, 09 Jul 2004 07:41:15 +0100
http://opencores.org/websvn,revision?repname=pci&path=%2Ftrunk%2F&rev=144
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Added SubsystemVendorID, SubsystemID, MAXLatency, MinGnt defines. ...
http://opencores.org/websvn,revision?repname=pci&path=%2Ftrunk%2F&rev=143
<div><strong>Rev 143 - mihad</strong> (4 file(s) modified)</div><div>Added SubsystemVendorID, SubsystemID, MAXLatency, MinGnt defines.<br />
Enabled value loading from serial ...</div>~ /trunk/bench/verilog/pci_regression_constants.v<br />~ /trunk/bench/verilog/system.v<br />~ /trunk/rtl/verilog/pci_conf_space.v<br />~ /trunk/rtl/verilog/pci_user_constants.v<br />
mihad
Wed, 07 Jul 2004 12:45:02 +0100
http://opencores.org/websvn,revision?repname=pci&path=%2Ftrunk%2F&rev=143
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Single PCI Master write fix.
http://opencores.org/websvn,revision?repname=pci&path=%2Ftrunk%2F&rev=142
<div><strong>Rev 142 - mihad</strong> (2 file(s) modified)</div><div>Single PCI Master write fix.</div>~ /trunk/bench/verilog/system.v<br />~ /trunk/rtl/verilog/pci_master32_sm_if.v<br />
mihad
Fri, 19 Mar 2004 16:36:55 +0100
http://opencores.org/websvn,revision?repname=pci&path=%2Ftrunk%2F&rev=142
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Update! SPOCI Implemented!
http://opencores.org/websvn,revision?repname=pci&path=%2Ftrunk%2F&rev=140
<div><strong>Rev 140 - mihad</strong> (20 file(s) modified)</div><div>Update! SPOCI Implemented!</div>~ /trunk/apps/sw/driver/pci_bridge32_test<br />~ /trunk/bench/verilog/pci_regression_constants.v<br />~ /trunk/bench/verilog/pci_unsupported_commands_master.v<br />~ /trunk/bench/verilog/system.v<br />~ /trunk/bench/verilog/top.v<br />~ /trunk/doc/pci_specification.doc<br />~ /trunk/doc/pci_specification.pdf<br />~ /trunk/rtl/verilog/pci_bridge32.v<br />~ /trunk/rtl/verilog/pci_conf_space.v<br />+ /trunk/rtl/verilog/pci_spoci_ctrl.v<br />~ /trunk/rtl/verilog/pci_user_constants.v<br />~ /trunk/rtl/verilog/pci_wbs_wbb3_2_wbb2.v<br />~ /trunk/rtl/verilog/pci_wb_master.v<br />~ /trunk/rtl/verilog/pci_wb_slave.v<br />~ /trunk/rtl/verilog/pci_wb_slave_unit.v<br />~ /trunk/sim/rtl_sim/bin/rtl_file_list.lst<br />~ /trunk/sim/rtl_sim/bin/sim_file_list.lst<br />~ /trunk/sim/rtl_sim/run/ncvlog.args<br />~ /trunk/sim/rtl_sim/run/run_pci_sim_regr.scr<br />~ /trunk/sim/rtl_sim/run/top_groups.do<br />
mihad
Sat, 24 Jan 2004 11:54:19 +0100
http://opencores.org/websvn,revision?repname=pci&path=%2Ftrunk%2F&rev=140
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Added for SPOCI testing!
http://opencores.org/websvn,revision?repname=pci&path=%2Ftrunk%2F&rev=139
<div><strong>Rev 139 - mihad</strong> (1 file(s) modified)</div><div>Added for SPOCI testing!</div>+ /trunk/bench/verilog/i2c_slave_model.v<br />
mihad
Sat, 24 Jan 2004 11:51:22 +0100
http://opencores.org/websvn,revision?repname=pci&path=%2Ftrunk%2F&rev=139
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added test_initial_all_conf_values
mbist_ctrl_i replaced by mbist_en_i
http://opencores.org/websvn,revision?repname=pci&path=%2Ftrunk%2F&rev=138
<div><strong>Rev 138 - fr2201</strong> (1 file(s) modified)</div><div>added test_initial_all_conf_values<br />
mbist_ctrl_i replaced by mbist_en_i</div>~ /trunk/bench/verilog/system.v<br />
fr2201
Wed, 07 Jan 2004 17:41:21 +0100
http://opencores.org/websvn,revision?repname=pci&path=%2Ftrunk%2F&rev=138
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def_wb_imagex_addr_map defined correctly
http://opencores.org/websvn,revision?repname=pci&path=%2Ftrunk%2F&rev=137
<div><strong>Rev 137 - fr2201</strong> (3 file(s) modified)</div><div>def_wb_imagex_addr_map defined correctly</div>~ /trunk/bench/verilog/system.v<br />~ /trunk/rtl/verilog/pci_conf_space.v<br />~ /trunk/rtl/verilog/pci_user_constants.v<br />
fr2201
Sun, 28 Dec 2003 09:54:48 +0100
http://opencores.org/websvn,revision?repname=pci&path=%2Ftrunk%2F&rev=137
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Reset values for PCI, WB defined (PCI_TAx,WB_BAx,WB_TAx,WB_AMx,WB_BAx_MEM_IO)
http://opencores.org/websvn,revision?repname=pci&path=%2Ftrunk%2F&rev=136
<div><strong>Rev 136 - fr2201</strong> (2 file(s) modified)</div><div>Reset values for PCI, WB defined (PCI_TAx,WB_BAx,WB_TAx,WB_AMx,WB_BAx_MEM_IO)</div>~ /trunk/rtl/verilog/pci_conf_space.v<br />~ /trunk/rtl/verilog/pci_user_constants.v<br />
fr2201
Sun, 28 Dec 2003 09:20:00 +0100
http://opencores.org/websvn,revision?repname=pci&path=%2Ftrunk%2F&rev=136
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Compact PCI Hot Swap support added.
New testcases added.
Specification updated.
Test application ...
http://opencores.org/websvn,revision?repname=pci&path=%2Ftrunk%2F&rev=132
<div><strong>Rev 132 - mihad</strong> (33 file(s) modified)</div><div>Compact PCI Hot Swap support added.<br />
New testcases added.<br />
Specification updated.<br />
Test application ...</div>~ /trunk/apps/test/rtl/verilog/pci_bridge32.v<br />~ /trunk/apps/test/rtl/verilog/pci_test_top_2clks.v<br />~ /trunk/apps/test/rtl/verilog/pci_user_constants.v<br />~ /trunk/apps/test/rtl/verilog/test.v<br />~ /trunk/apps/test/syn/synplify/pci_test_top.prj<br />~ /trunk/apps/test/syn/synplify/pci_test_top.ucf<br />~ /trunk/apps/test/syn/synplify/pci_test_top_2clks.sdc<br />~ /trunk/bench/verilog/pci_behaviorial_master.v<br />~ /trunk/bench/verilog/pci_bench_common_tasks.v<br />~ /trunk/bench/verilog/pci_regression_constants.v<br />~ /trunk/bench/verilog/pci_testbench_defines.v<br />~ /trunk/bench/verilog/system.v<br />~ /trunk/doc/pci_specification.doc<br />~ /trunk/doc/pci_specification.pdf<br />~ /trunk/rtl/verilog/pci_bridge32.v<br />~ /trunk/rtl/verilog/pci_conf_space.v<br />~ /trunk/rtl/verilog/pci_constants.v<br />~ /trunk/rtl/verilog/pci_in_reg.v<br />~ /trunk/rtl/verilog/pci_io_mux.v<br />~ /trunk/rtl/verilog/pci_master32_sm_if.v<br />~ /trunk/rtl/verilog/pci_rst_int.v<br />~ /trunk/rtl/verilog/pci_target32_interface.v<br />~ /trunk/rtl/verilog/pci_target32_sm.v<br />~ /trunk/rtl/verilog/pci_target_unit.v<br />~ /trunk/rtl/verilog/pci_user_constants.v<br />~ /trunk/rtl/verilog/pci_wbs_wbb3_2_wbb2.v<br />~ /trunk/rtl/verilog/pci_wbw_wbr_fifos.v<br />~ /trunk/rtl/verilog/pci_wb_slave.v<br />~ /trunk/sim/rtl_sim/bin/hdl.var<br />~ /trunk/sim/rtl_sim/log/get_log_err_war<br />~ /trunk/sim/rtl_sim/run/ncelab.args<br />~ /trunk/sim/rtl_sim/run/run_pci_sim_regr.scr<br />~ /trunk/sim/rtl_sim/run/top_groups.do<br />
mihad
Fri, 19 Dec 2003 11:11:32 +0100
http://opencores.org/websvn,revision?repname=pci&path=%2Ftrunk%2F&rev=132
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Moved top.v to bench directory. Removed unneeded meta_flop,
modified files list ...
http://opencores.org/websvn,revision?repname=pci&path=%2Ftrunk%2F&rev=131
<div><strong>Rev 131 - mihad</strong> (5 file(s) modified)</div><div>Moved top.v to bench directory. Removed unneeded meta_flop,<br />
modified files list ...</div>+ /trunk/bench/verilog/top.v<br />- /trunk/rtl/verilog/meta_flop.v<br />- /trunk/rtl/verilog/top.v<br />~ /trunk/sim/rtl_sim/bin/rtl_file_list.lst<br />~ /trunk/sim/rtl_sim/bin/sim_file_list.lst<br />
mihad
Mon, 15 Dec 2003 12:25:26 +0100
http://opencores.org/websvn,revision?repname=pci&path=%2Ftrunk%2F&rev=131
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