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sdr_ctrl WebSVN RSS feed - sdr_ctrl http://opencores.org/websvn,listing?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F& Sun, 26 May 2013 06:13:44 +0100 FeedCreator 1.7.2 test bench upgrade + rtl cleanup http://opencores.org/websvn,revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=46 <div><strong>Rev 46 - dinesha</strong> (17 file(s) modified)</div><div>test bench upgrade + rtl cleanup</div>~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v<br />~ /sdr_ctrl/trunk/rtl/top/sdrc_top.v<br />~ /sdr_ctrl/trunk/verif/log/core_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/tb/tb_core.sv<br />~ /sdr_ctrl/trunk/verif/tb/tb_top.sv<br /> dinesha Sat, 04 Feb 2012 10:36:22 +0100 http://opencores.org/websvn,revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=46 RTL clean up and logic seperation done from sdram bus ... http://opencores.org/websvn,revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=45 <div><strong>Rev 45 - dinesha</strong> (19 file(s) modified)</div><div>RTL clean up and logic seperation done from sdram bus ...</div>~ /sdr_ctrl/trunk/rtl/core/sdrc_bs_convert.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v<br />~ /sdr_ctrl/trunk/verif/log/core_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/run/read.me<br />~ /sdr_ctrl/trunk/verif/tb/tb_core.sv<br />~ /sdr_ctrl/trunk/verif/tb/tb_top.sv<br /> dinesha Sat, 04 Feb 2012 06:17:34 +0100 http://opencores.org/websvn,revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=45 SDRAM data path logic is modified to support 4 command ... http://opencores.org/websvn,revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=44 <div><strong>Rev 44 - dinesha</strong> (8 file(s) modified)</div><div>SDRAM data path logic is modified to support 4 command ...</div>~ /sdr_ctrl/trunk/rtl/core/sdrc_bs_convert.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />~ /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/tb/tb_core.sv<br />~ /sdr_ctrl/trunk/verif/tb/tb_top.sv<br /> dinesha Thu, 02 Feb 2012 08:12:21 +0100 http://opencores.org/websvn,revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=44 Test bench automation to handle differ write/read burst sequence is ... http://opencores.org/websvn,revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=43 <div><strong>Rev 43 - dinesha</strong> (15 file(s) modified)</div><div>Test bench automation to handle differ write/read burst sequence is ...</div>~ /sdr_ctrl/trunk/verif/log/core_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/run/run_modelsim<br />~ /sdr_ctrl/trunk/verif/tb/tb_core.sv<br />~ /sdr_ctrl/trunk/verif/tb/tb_top.sv<br /> dinesha Thu, 02 Feb 2012 06:27:19 +0100 http://opencores.org/websvn,revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=43 Bug fix in read access is fixed http://opencores.org/websvn,revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=42 <div><strong>Rev 42 - dinesha</strong> (1 file(s) modified)</div><div>Bug fix in read access is fixed</div>~ /sdr_ctrl/trunk/rtl/wb2sdrc/wb2sdrc.v<br /> dinesha Thu, 02 Feb 2012 06:22:39 +0100 http://opencores.org/websvn,revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=42 Updated Spec ver 0.1 is added back to svn http://opencores.org/websvn,revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=41 <div><strong>Rev 41 - dinesha</strong> (1 file(s) modified)</div><div>Updated Spec ver 0.1 is added back to svn</div>~ /sdr_ctrl/trunk/doc/sdram_controller_specs.pdf<br /> dinesha Thu, 02 Feb 2012 04:44:26 +0100 http://opencores.org/websvn,revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=41 Application layer Fifo full conditional are register now to synth ... http://opencores.org/websvn,revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=40 <div><strong>Rev 40 - dinesha</strong> (1 file(s) modified)</div><div>Application layer Fifo full conditional are register now to synth ...</div>~ /sdr_ctrl/trunk/rtl/wb2sdrc/wb2sdrc.v<br /> dinesha Wed, 01 Feb 2012 11:46:29 +0100 http://opencores.org/websvn,revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=40 Test Bench upgradation with bigger data burst size http://opencores.org/websvn,revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=39 <div><strong>Rev 39 - dinesha</strong> (7 file(s) modified)</div><div>Test Bench upgradation with bigger data burst size</div>~ /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/tb/tb_top.sv<br /> dinesha Wed, 01 Feb 2012 11:39:09 +0100 http://opencores.org/websvn,revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=39 Port Name clean up http://opencores.org/websvn,revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=38 <div><strong>Rev 38 - dinesha</strong> (2 file(s) modified)</div><div>Port Name clean up</div>~ /sdr_ctrl/trunk/rtl/top/sdrc_top.v<br />~ /sdr_ctrl/trunk/verif/tb/tb_top.sv<br /> dinesha Tue, 31 Jan 2012 06:38:02 +0100 http://opencores.org/websvn,revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=38 SDRAM dq and sdram pad clock are termindated inside the ... http://opencores.org/websvn,revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=37 <div><strong>Rev 37 - dinesha</strong> (17 file(s) modified)</div><div>SDRAM dq and sdram pad clock are termindated inside the ...</div>- /sdr_ctrl/trunk/rtl/core/sdrc.def<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_bank_fsm.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_bs_convert.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />+ /sdr_ctrl/trunk/rtl/core/sdrc_define.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v<br />~ /sdr_ctrl/trunk/rtl/top/sdrc_top.v<br />~ /sdr_ctrl/trunk/rtl/wb2sdrc/wb2sdrc.v<br />~ /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/tb/tb_top.sv<br /> dinesha Tue, 31 Jan 2012 04:53:16 +0100 http://opencores.org/websvn,revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=37 Clean up http://opencores.org/websvn,revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=36 <div><strong>Rev 36 - dinesha</strong> (1 file(s) modified)</div><div>Clean up</div>~ /sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v<br /> dinesha Mon, 30 Jan 2012 14:03:08 +0100 http://opencores.org/websvn,revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=36 Updated the New Documents - ver 0.1 http://opencores.org/websvn,revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=35 <div><strong>Rev 35 - dinesha</strong> (1 file(s) modified)</div><div>Updated the New Documents - ver 0.1</div>+ /sdr_ctrl/trunk/doc/sdram_controller_specs.pdf<br /> dinesha Mon, 30 Jan 2012 12:26:17 +0100 http://opencores.org/websvn,revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=35 Removed the older version http://opencores.org/websvn,revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=34 <div><strong>Rev 34 - dinesha</strong> (1 file(s) modified)</div><div>Removed the older version</div>- /sdr_ctrl/trunk/doc/sdram_controller_specs.pdf<br /> dinesha Mon, 30 Jan 2012 12:23:59 +0100 http://opencores.org/websvn,revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=34 clean up http://opencores.org/websvn,revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=33 <div><strong>Rev 33 - dinesha</strong> (6 file(s) modified)</div><div>clean up</div>~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v<br />~ /sdr_ctrl/trunk/rtl/top/sdrc_top.v<br />~ /sdr_ctrl/trunk/rtl/wb2sdrc/wb2sdrc.v<br />+ /sdr_ctrl/trunk/verif/run/regression_analysis<br />~ /sdr_ctrl/trunk/verif/run/run_all<br /> dinesha Mon, 30 Jan 2012 11:54:32 +0100 http://opencores.org/websvn,revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=33 Debug is enable through +define http://opencores.org/websvn,revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=32 <div><strong>Rev 32 - dinesha</strong> (1 file(s) modified)</div><div>Debug is enable through +define</div>~ /sdr_ctrl/trunk/verif/model/mt48lc8m8a2.v<br /> dinesha Sat, 28 Jan 2012 12:58:53 +0100 http://opencores.org/websvn,revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=32 Integrated SDRAM controller with wishbone interface is added into SVN http://opencores.org/websvn,revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=31 <div><strong>Rev 31 - dinesha</strong> (8 file(s) modified)</div><div>Integrated SDRAM controller with wishbone interface is added into SVN</div>~ /sdr_ctrl/trunk/rtl/core/sdrc_bs_convert.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />+ /sdr_ctrl/trunk/rtl/lib/async_fifo.v<br />+ /sdr_ctrl/trunk/rtl/lib/sync_fifo.v<br />+ /sdr_ctrl/trunk/rtl/top<br />+ /sdr_ctrl/trunk/rtl/top/sdrc_top.v<br />+ /sdr_ctrl/trunk/rtl/wb2sdrc<br />+ /sdr_ctrl/trunk/rtl/wb2sdrc/wb2sdrc.v<br /> dinesha Sat, 28 Jan 2012 12:56:29 +0100 http://opencores.org/websvn,revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=31 test bench file for integrated SDRAM controller with wish bone ... http://opencores.org/websvn,revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=30 <div><strong>Rev 30 - dinesha</strong> (2 file(s) modified)</div><div>test bench file for integrated SDRAM controller with wish bone ...</div>+ /sdr_ctrl/trunk/verif/tb/tb_core.sv<br />~ /sdr_ctrl/trunk/verif/tb/tb_top.sv<br /> dinesha Sat, 28 Jan 2012 12:46:31 +0100 http://opencores.org/websvn,revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=30 SDRAM top and core related run file list are added ... http://opencores.org/websvn,revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=29 <div><strong>Rev 29 - dinesha</strong> (6 file(s) modified)</div><div>SDRAM top and core related run file list are added ...</div>~ /sdr_ctrl/trunk/verif/run/compile.modelsim<br />+ /sdr_ctrl/trunk/verif/run/filelist_core.f<br />+ /sdr_ctrl/trunk/verif/run/filelist_rtl.f<br />+ /sdr_ctrl/trunk/verif/run/filelist_top.f<br />~ /sdr_ctrl/trunk/verif/run/run_all<br />~ /sdr_ctrl/trunk/verif/run/run_modelsim<br /> dinesha Sat, 28 Jan 2012 12:43:55 +0100 http://opencores.org/websvn,revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=29 SDRAM top and SDRAM Core Golden files are added into ... http://opencores.org/websvn,revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=28 <div><strong>Rev 28 - dinesha</strong> (15 file(s) modified)</div><div>SDRAM top and SDRAM Core Golden files are added into ...</div>~ /sdr_ctrl/trunk/verif/log/core_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_32BIT_basic_test1.log<br />+ /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log<br />+ /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log<br />+ /sdr_ctrl/trunk/verif/log/top_sdr32_sim.log<br />+ /sdr_ctrl/trunk/verif/log/top_SDR_8BIT_basic_test1.log<br />+ /sdr_ctrl/trunk/verif/log/top_SDR_8BIT_complie.log<br />+ /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log<br />+ /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_complie.log<br />+ /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log<br />+ /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_complie.log<br /> dinesha Sat, 28 Jan 2012 12:38:25 +0100 http://opencores.org/websvn,revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=28 Golden log file corresponds the SDRAM core level test case ... http://opencores.org/websvn,revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=27 <div><strong>Rev 27 - dinesha</strong> (9 file(s) modified)</div><div>Golden log file corresponds the SDRAM core level test case ...</div>+ /sdr_ctrl/trunk/verif/log/core_sdr8_sim.log<br />+ /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log<br />+ /sdr_ctrl/trunk/verif/log/core_sdr32_sim.log<br />+ /sdr_ctrl/trunk/verif/log/core_SDR_8BIT_basic_test1.log<br />+ /sdr_ctrl/trunk/verif/log/core_SDR_8BIT_complie.log<br />+ /sdr_ctrl/trunk/verif/log/core_SDR_16BIT_basic_test1.log<br />+ /sdr_ctrl/trunk/verif/log/core_SDR_16BIT_complie.log<br />+ /sdr_ctrl/trunk/verif/log/core_SDR_32BIT_basic_test1.log<br />+ /sdr_ctrl/trunk/verif/log/core_SDR_32BIT_complie.log<br /> dinesha Fri, 27 Jan 2012 14:33:55 +0100 http://opencores.org/websvn,revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=27

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