部分翻译
Error creating feed file, please check write permissions.
socgen
WebSVN RSS feed - socgen
http://opencores.org/websvn,listing?repname=socgen&path=%2Fsocgen%2Ftrunk%2Ftools%2Forbuild%2F&
Thu, 23 May 2013 13:22:11 +0100
FeedCreator 1.7.2
-
added build_header
now use build_register for all spr components
resynced or1200 code ...
http://opencores.org/websvn,revision?repname=socgen&path=%2Fsocgen%2Ftrunk%2Ftools%2Forbuild%2F&rev=116
<div><strong>Rev 116 - jt_eaton</strong> (292 file(s) modified)</div><div>added build_header<br />
now use build_register for all spr components<br />
resynced or1200 code ...</div>- /socgen/trunk/projects/opencores.org/cde/ip/cde_sram/ip-xact/cde_sram_def.designCfg.xml<br />- /socgen/trunk/projects/opencores.org/cde/ip/cde_sram/ip-xact/cde_sram_dp.designCfg.xml<br />~ /socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/verilog/sim/cde_sram_be.v<br />~ /socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/verilog/syn/cde_sram_be.v<br />~ /socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/xml/cde_sram_be.xml<br />- /socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/xml/cde_sram_def.design.xml<br />- /socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/xml/cde_sram_dp.design.xml<br />~ /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_core.xml<br />~ /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_default.xml<br />~ /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_io_irq_2.xml<br />~ /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_io_poll_2.xml<br />~ /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_irq_2_test.xml<br />~ /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_kim_2.xml<br />~ /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_tim_2.xml<br />~ /socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/sim/icarus/uart-nocache_emb/wave.sav<br />~ /socgen/trunk/projects/opencores.org/io/ip/io_ext_mem_interface/rtl/verilog/top.body<br />~ /socgen/trunk/projects/opencores.org/io/ip/io_ext_mem_interface/rtl/xml/io_ext_mem_interface_def.xml<br />~ /socgen/trunk/projects/opencores.org/io/ip/io_ext_mem_interface/sim/xml/io_ext_mem_interface_tb.xml<br />~ /socgen/trunk/projects/opencores.org/io/ip/io_gpio/rtl/verilog/top.body<br />~ /socgen/trunk/projects/opencores.org/io/ip/io_gpio/rtl/xml/io_gpio_def.xml<br />~ /socgen/trunk/projects/opencores.org/io/ip/io_gpio/sim/xml/io_gpio_tb.xml<br />~ /socgen/trunk/projects/opencores.org/io/ip/io_module/rtl/xml/io_module_def.xml<br />~ /socgen/trunk/projects/opencores.org/io/ip/io_module/rtl/xml/io_module_gpio.xml<br />~ /socgen/trunk/projects/opencores.org/io/ip/io_module/rtl/xml/io_module_mouse.xml<br />~ /socgen/trunk/projects/opencores.org/io/ip/io_module/sim/xml/io_module_gpio_tb.design.xml<br />~ /socgen/trunk/projects/opencores.org/io/ip/io_module/sim/xml/io_module_gpio_tb.xml<br />~ /socgen/trunk/projects/opencores.org/io/ip/io_module/sim/xml/io_module_mouse_tb.design.xml<br />~ /socgen/trunk/projects/opencores.org/io/ip/io_module/sim/xml/io_module_mouse_tb.xml<br />~ /socgen/trunk/projects/opencores.org/io/ip/io_module/sim/xml/io_module_tb.design.xml<br />~ /socgen/trunk/projects/opencores.org/io/ip/io_pic/rtl/verilog/top.body<br />~ /socgen/trunk/projects/opencores.org/io/ip/io_pic/rtl/xml/io_pic_def.xml<br />~ /socgen/trunk/projects/opencores.org/io/ip/io_pic/sim/xml/io_pic_tb.xml<br />~ /socgen/trunk/projects/opencores.org/io/ip/io_ps2/ip-xact/design.xml<br />~ /socgen/trunk/projects/opencores.org/io/ip/io_ps2/rtl/verilog/top.body<br />~ /socgen/trunk/projects/opencores.org/io/ip/io_ps2/rtl/xml/io_ps2_def.xml<br />~ /socgen/trunk/projects/opencores.org/io/ip/io_ps2/rtl/xml/io_ps2_mouse.xml<br />~ /socgen/trunk/projects/opencores.org/io/ip/io_ps2/sim/icarus/default/test_define<br />~ /socgen/trunk/projects/opencores.org/io/ip/io_ps2/sim/icarus/mouse_default/test_define<br />~ /socgen/trunk/projects/opencores.org/io/ip/io_ps2/sim/verilog/tb.ext<br />~ /socgen/trunk/projects/opencores.org/io/ip/io_ps2/sim/xml/io_ps2_mouse_tb.design.xml<br />~ /socgen/trunk/projects/opencores.org/io/ip/io_ps2/sim/xml/io_ps2_mouse_tb.xml<br />~ /socgen/trunk/projects/opencores.org/io/ip/io_ps2/sim/xml/io_ps2_tb.design.xml<br />~ /socgen/trunk/projects/opencores.org/io/ip/io_ps2/sim/xml/io_ps2_tb.xml<br />~ /socgen/trunk/projects/opencores.org/io/ip/io_timer/rtl/verilog/top.body<br />~ /socgen/trunk/projects/opencores.org/io/ip/io_timer/rtl/xml/io_timer_def.xml<br />~ /socgen/trunk/projects/opencores.org/io/ip/io_timer/sim/xml/io_timer_tb.xml<br />~ /socgen/trunk/projects/opencores.org/io/ip/io_uart/rtl/verilog/top.body<br />~ /socgen/trunk/projects/opencores.org/io/ip/io_uart/rtl/xml/io_uart_def.xml<br />~ /socgen/trunk/projects/opencores.org/io/ip/io_uart/rtl/xml/io_uart_rx.xml<br />~ /socgen/trunk/projects/opencores.org/io/ip/io_uart/rtl/xml/io_uart_rxtx.xml<br />~ /socgen/trunk/projects/opencores.org/io/ip/io_uart/rtl/xml/io_uart_tx.xml<br />~ /socgen/trunk/projects/opencores.org/io/ip/io_uart/sim/xml/io_uart_rxtx_tb.xml<br />~ /socgen/trunk/projects/opencores.org/io/ip/io_uart/sim/xml/io_uart_rx_tb.xml<br />~ /socgen/trunk/projects/opencores.org/io/ip/io_uart/sim/xml/io_uart_tb.xml<br />~ /socgen/trunk/projects/opencores.org/io/ip/io_uart/sim/xml/io_uart_tx_tb.xml<br />~ /socgen/trunk/projects/opencores.org/io/ip/io_utimer/rtl/verilog/top.body<br />~ /socgen/trunk/projects/opencores.org/io/ip/io_utimer/rtl/xml/io_utimer_def.xml<br />~ /socgen/trunk/projects/opencores.org/io/ip/io_utimer/sim/xml/io_utimer_tb.xml<br />~ /socgen/trunk/projects/opencores.org/io/ip/io_vga/rtl/verilog/top.body<br />~ /socgen/trunk/projects/opencores.org/io/ip/io_vga/rtl/xml/io_vga_def.xml<br />~ /socgen/trunk/projects/opencores.org/io/ip/io_vga/sim/xml/io_vga_tb.xml<br />~ /socgen/trunk/projects/opencores.org/io/ip/io_vic/rtl/verilog/top.body<br />~ /socgen/trunk/projects/opencores.org/io/ip/io_vic/rtl/xml/io_vic_def.xml<br />~ /socgen/trunk/projects/opencores.org/io/ip/io_vic/sim/xml/io_vic_tb.xml<br />~ /socgen/trunk/projects/opencores.org/or1k/bin/compile<br />~ /socgen/trunk/projects/opencores.org/or1k/bin/Makefile.or32<br />~ /socgen/trunk/projects/opencores.org/or1k/doc/pdf/journal.pdf<br />~ /socgen/trunk/projects/opencores.org/or1k/doc/src/journal.html<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200/ip-xact/design.xml<br />+ /socgen/trunk/projects/opencores.org/or1k/ip/or1200/ip-xact/or1200_null.designCfg.xml<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/verilog/or1200_monitor.v<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/verilog/or1200_monitor_defines.v<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/verilog/top.or1200_mon<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/xml/or1200_clkgen.xml<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/xml/or1200_dbg.design.xml<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/xml/or1200_dbg.xml<br />+ /socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/xml/or1200_null.design.xml<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-basic/wave.sav<br />+ /socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-dsx<br />+ /socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-dsx/dmp_define<br />+ /socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-dsx/test_define<br />+ /socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-dsx/wave.sav<br />+ /socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-dsxinsn<br />+ /socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-dsxinsn/dmp_define<br />+ /socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-dsxinsn/test_define<br />+ /socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-dsxinsn/wave.sav<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-float/wave.sav<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-fp/test_define<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-fp/wave.sav<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-mac/wave.sav<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-maci/wave.sav<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-no_code_sprs_sys/test_define<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-no_code_sprs_sys/wave.sav<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-tick/wave.sav<br />+ /socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200_q-basic<br />+ /socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200_q-basic/dmp_define<br />+ /socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200_q-basic/test_define<br />+ /socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200_q-basic/wave.sav<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/xml/or1200_dbg_tb.design.xml<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/xml/or1200_dbg_tb.xml<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/or1200_dc_fsm.v<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/or1200_ic_fsm.v<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/top.data<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/xml/or1200_cache_data.xml<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/xml/or1200_cache_inst.xml<br />+ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/cache_en<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/cpu_cfgr<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/cpu_except<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/cpu_genpc<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/cpu_lsu<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/cpu_rf<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/cpu_sprs<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/cpu_spr_mux<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/defines<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_alu.xml<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_boot.xml<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_cfgr.xml<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_ctrl.xml<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_dbg.xml<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_def.design.xml<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_du.xml<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_except.xml<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_freeze.xml<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_genpc.xml<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_if.xml<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_lsu.xml<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_operandmuxes.xml<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_rf.xml<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_sprs.xml<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_spr_mux.xml<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_wbmux.xml<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_fpu/rtl/verilog/top.def<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_fpu/rtl/xml/or1200_fpu_def.xml<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/verilog/or1200_dmmu_tlb.v<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/verilog/or1200_immu_tlb.v<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/verilog/top.data<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/verilog/top.inst<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/xml/or1200_mmu_data.xml<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/xml/or1200_mmu_inst.xml<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_mult_mac/rtl/verilog/top.def<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_mult_mac/rtl/xml/or1200_mult_mac_asic.xml<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_mult_mac/rtl/xml/or1200_mult_mac_def.xml<br />- /socgen/trunk/projects/opencores.org/or1k/ip/or1200_pic/rtl/verilog/top<br />+ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_pic/rtl/verilog/top.def<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_pic/rtl/xml/or1200_pic_def.xml<br />- /socgen/trunk/projects/opencores.org/or1k/ip/or1200_pm/rtl/verilog/top<br />+ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_pm/rtl/verilog/top.def<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_pm/rtl/xml/or1200_pm_def.xml<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_qmem/ip-xact/design.xml<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_qmem/rtl/verilog/defines<br />- /socgen/trunk/projects/opencores.org/or1k/ip/or1200_qmem/rtl/verilog/or1200_spram_2048x32.v<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_qmem/rtl/verilog/top.def<br />- /socgen/trunk/projects/opencores.org/or1k/ip/or1200_qmem/rtl/verilog/top.split<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_qmem/rtl/xml/or1200_qmem_def.xml<br />- /socgen/trunk/projects/opencores.org/or1k/ip/or1200_qmem/rtl/xml/or1200_qmem_split.xml<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_sb/rtl/xml/or1200_sb_def.xml<br />- /socgen/trunk/projects/opencores.org/or1k/ip/or1200_tt/rtl/verilog/top<br />+ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_tt/rtl/verilog/top.def<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_tt/rtl/xml/or1200_tt_def.xml<br />~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_wb_biu/rtl/xml/or1200_wb_biu_def.xml<br />~ /socgen/trunk/projects/opencores.org/or1k/sw/backend/link.ld<br />~ /socgen/trunk/projects/opencores.org/or1k/sw/cache/cache.S<br />~ /socgen/trunk/projects/opencores.org/or1k/sw/crt0/crt0.S<br />~ /socgen/trunk/projects/opencores.org/or1k/sw/intgen-intsyscall/intgen-intsyscall.S<br />~ /socgen/trunk/projects/opencores.org/or1k/sw/intgen-ticksyscall/intgen-ticksyscall.S<br />~ /socgen/trunk/projects/opencores.org/or1k/sw/mmu/mmu.S<br />~ /socgen/trunk/projects/opencores.org/or1k/sw/or1200-basic/or1200-basic.S<br />~ /socgen/trunk/projects/opencores.org/or1k/sw/or1200-cy/or1200-cy.S<br />~ /socgen/trunk/projects/opencores.org/or1k/sw/or1200-dctest/Makefile<br />~ /socgen/trunk/projects/opencores.org/or1k/sw/or1200-div/Makefile<br />+ /socgen/trunk/projects/opencores.org/or1k/sw/or1200-dsx<br />+ /socgen/trunk/projects/opencores.org/or1k/sw/or1200-dsx/Makefile<br />+ /socgen/trunk/projects/opencores.org/or1k/sw/or1200-dsx/or1200-dsx.S<br />+ /socgen/trunk/projects/opencores.org/or1k/sw/or1200-dsxinsn<br />+ /socgen/trunk/projects/opencores.org/or1k/sw/or1200-dsxinsn/Makefile<br />+ /socgen/trunk/projects/opencores.org/or1k/sw/or1200-dsxinsn/or1200-dsxinsn.S<br />~ /socgen/trunk/projects/opencores.org/or1k/sw/or1200-except/or1200-except.S<br />~ /socgen/trunk/projects/opencores.org/or1k/sw/or1200-ext/or1200-ext.S<br />~ /socgen/trunk/projects/opencores.org/or1k/sw/or1200-ffl1/or1200-ffl1.S<br />~ /socgen/trunk/projects/opencores.org/or1k/sw/or1200-float/Makefile<br />~ /socgen/trunk/projects/opencores.org/or1k/sw/or1200-fp/or1200-fp.S<br />~ /socgen/trunk/projects/opencores.org/or1k/sw/or1200-mac/or1200-mac.S<br />~ /socgen/trunk/projects/opencores.org/or1k/sw/or1200-maci/or1200-maci.S<br />~ /socgen/trunk/projects/opencores.org/or1k/sw/or1200-mmu/Makefile<br />~ /socgen/trunk/projects/opencores.org/or1k/sw/or1200-mul/Makefile<br />~ /socgen/trunk/projects/opencores.org/or1k/sw/or1200-ov/or1200-ov.S<br />~ /socgen/trunk/projects/opencores.org/or1k/sw/or1200-pm/or1200-pm.S<br />~ /socgen/trunk/projects/opencores.org/or1k/sw/or1200-qmem/or1200-qmem.S<br />~ /socgen/trunk/projects/opencores.org/or1k/sw/or1200-rfe/or1200-rfe.S<br />~ /socgen/trunk/projects/opencores.org/or1k/sw/or1200-rfemmu/or1200-rfemmu.S<br />~ /socgen/trunk/projects/opencores.org/or1k/sw/or1200-sb/or1200-sb.S<br />~ /socgen/trunk/projects/opencores.org/or1k/sw/or1200-simple/Makefile<br />~ /socgen/trunk/projects/opencores.org/or1k/sw/or1200-tick/or1200-tick.S<br />- /socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-basic<br />- /socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-cbasic<br />- /socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-cy<br />- /socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-dctest<br />- /socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-except<br />- /socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-ext<br />- /socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-ffl1<br />- /socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-float<br />- /socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-fp<br />- /socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-intsyscall<br />- /socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-linkregtest<br />- /socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-mac<br />- /socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-maci<br />- /socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-mmu<br />- /socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-ov<br />- /socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-rfe<br />- /socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-rfemmu<br />- /socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-sf<br />- /socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-simple<br />- /socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-tick<br />- /socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-ticksyscall<br />- /socgen/trunk/projects/opencores.org/orp_soc/ip/or1200<br />~ /socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/rtl/verilog/top.rtl<br />- /socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/sim/icarus/or1200-intsyscall<br />- /socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/sim/icarus/or1200-ticksyscall<br />~ /socgen/trunk/projects/opencores.org/orp_soc/sw/backend/link.ld<br />~ /socgen/trunk/projects/opencores.org/orp_soc/sw/crt0/crt0.S<br />~ /socgen/trunk/projects/opencores.org/orp_soc/sw/intgen-intsyscall/intgen-intsyscall.S<br />~ /socgen/trunk/projects/opencores.org/orp_soc/sw/intgen-ticksyscall/intgen-ticksyscall.S<br />~ /socgen/trunk/projects/opencores.org/orp_soc/sw/mmu/mmu.S<br />~ /socgen/trunk/projects/opencores.org/orp_soc/sw/or1200-basic/or1200-basic.S<br />~ /socgen/trunk/projects/opencores.org/orp_soc/sw/or1200-cy/or1200-cy.S<br />~ /socgen/trunk/projects/opencores.org/orp_soc/sw/or1200-except/or1200-except.S<br />~ /socgen/trunk/projects/opencores.org/orp_soc/sw/or1200-ext/or1200-ext.S<br />~ /socgen/trunk/projects/opencores.org/orp_soc/sw/or1200-ffl1/or1200-ffl1.S<br />~ /socgen/trunk/projects/opencores.org/orp_soc/sw/or1200-fp/or1200-fp.S<br />- /socgen/trunk/projects/opencores.org/orp_soc/sw/or1200-intsyscall<br />~ /socgen/trunk/projects/opencores.org/orp_soc/sw/or1200-linkregtest/or1200-linkregtest.S<br />~ /socgen/trunk/projects/opencores.org/orp_soc/sw/or1200-mac/or1200-mac.S<br />~ /socgen/trunk/projects/opencores.org/orp_soc/sw/or1200-maci/or1200-maci.S<br />~ /socgen/trunk/projects/opencores.org/orp_soc/sw/or1200-ov/or1200-ov.S<br />~ /socgen/trunk/projects/opencores.org/orp_soc/sw/or1200-pm/or1200-pm.S<br />~ /socgen/trunk/projects/opencores.org/orp_soc/sw/or1200-qmem/or1200-qmem.S<br />~ /socgen/trunk/projects/opencores.org/orp_soc/sw/or1200-rfe/or1200-rfe.S<br />~ /socgen/trunk/projects/opencores.org/orp_soc/sw/or1200-rfemmu/or1200-rfemmu.S<br />~ /socgen/trunk/projects/opencores.org/orp_soc/sw/or1200-sb/or1200-sb.S<br />~ /socgen/trunk/projects/opencores.org/orp_soc/sw/or1200-sf/or1200-sf.S<br />~ /socgen/trunk/projects/opencores.org/orp_soc/sw/or1200-tick/or1200-tick.S<br />- /socgen/trunk/projects/opencores.org/orp_soc/sw/or1200-ticksyscall<br />~ /socgen/trunk/projects/opencores.org/Testbench/ip/micro_bus_model/rtl/verilog/sim/top<br />~ /socgen/trunk/projects/opencores.org/Testbench/ip/micro_bus_model/rtl/verilog/syn/top<br />~ /socgen/trunk/projects/opencores.org/Testbench/ip/micro_bus_model/rtl/xml/micro_bus_model_def.xml<br />~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_memory/rtl/verilog/top.body<br />~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_memory/rtl/xml/wb_memory_def.design.xml<br />~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_memory/rtl/xml/wb_memory_def.xml<br />~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_ram/rtl/xml/wb_ram_def.xml<br />- /socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/ip-xact/wb_traffic_cop_def.designCfg.xml<br />- /socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/rtl/xml/wb_traffic_cop_def.design.xml<br />~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/rtl/xml/wb_traffic_cop_def.xml<br />~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/sim/xml/wb_traffic_cop_tb.design.xml<br />~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/ip-xact/design.xml<br />- /socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/rtl/variants<br />~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/rtl/verilog/top.body<br />~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/rtl/xml/wb_uart16550_bus16_big.xml<br />~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/rtl/xml/wb_uart16550_bus16_lit.xml<br />~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/rtl/xml/wb_uart16550_bus32_big.xml<br />~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/rtl/xml/wb_uart16550_bus32_lit.xml<br />~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/rtl/xml/wb_uart16550_def.xml<br />~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/icarus/bus16_big_default/test_define<br />~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/icarus/bus16_lit_default/test_define<br />~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/icarus/bus32_big_default/test_define<br />~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/icarus/bus32_lit_default/test_define<br />~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/icarus/default/test_define<br />~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/xml/wb_uart16550_bus16_big_tb.xml<br />~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/xml/wb_uart16550_bus16_lit_tb.xml<br />~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/xml/wb_uart16550_bus32_big_tb.xml<br />~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/xml/wb_uart16550_bus32_lit_tb.xml<br />~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/xml/wb_uart16550_tb.xml<br />- /socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/soc<br />~ /socgen/trunk/projects/opencores.org/xfer/ip/minsoc/rtl/xml/minsoc_def.design.xml<br />~ /socgen/trunk/projects/opencores.org/xfer/sw/basic/basic.S<br />~ /socgen/trunk/projects/opencores.org/xfer/sw/or1200-basic/or1200-basic.S<br />~ /socgen/trunk/projects/opencores.org/xfer/sw/support/support.c<br />+ /socgen/trunk/tools/install/Ubuntu_12.04<br />+ /socgen/trunk/tools/install/Ubuntu_12.04/Makefile<br />+ /socgen/trunk/tools/install/Ubuntu_12.04/README.txt<br />- /socgen/trunk/tools/or32-elf<br />+ /socgen/trunk/tools/orbuild<br />+ /socgen/trunk/tools/orbuild/Makefile<br />+ /socgen/trunk/tools/orbuild/orbuild.conf<br />+ /socgen/trunk/tools/orbuild/orbuild_Scripts_Projects_OpenRISC_makefile<br />+ /socgen/trunk/tools/orbuild/README<br />~ /socgen/trunk/tools/sys/build_geda<br />+ /socgen/trunk/tools/sys/build_header<br />~ /socgen/trunk/tools/sys/build_registers<br />~ /socgen/trunk/tools/sys/build_verilog<br />~ /socgen/trunk/tools/sys/build_verilogLibraryFile<br />~ /socgen/trunk/tools/sys/soc_generate<br />~ /socgen/trunk/tools/utils/bin2abs.c<br />
jt_eaton
Tue, 12 Jun 2012 01:01:04 +0100
http://opencores.org/websvn,revision?repname=socgen&path=%2Fsocgen%2Ftrunk%2Ftools%2Forbuild%2F&rev=116
© copyright 1999-2013
OpenCores.org, equivalent to ORSoC AB, all rights reserved. OpenCores®, registered trademark.