AC Entity Reference

Inheritance diagram for AC:
behave struct MP

List of all members.



Architectures

behave Architecture

Libraries

ieee 

Packages

std_logic_1164 
std_logic_arith 
std_logic_unsigned 

Ports

d  in std_logic_vector ( 7 downto 0 )
 8-bit input data to AC from W-bus
q_alu  out std_logic_vector ( 7 downto 0 )
 8-bit output data to AC from W-bus
q_data  out std_logic_vector ( 7 downto 0 )
 8-bit output data to Adder-Subtractor block
clk  in std_logic
 Rising edge clock.
ea  in std_logic
 Active high enable AC control input signal.
clr  in std_logic
 Active high asynchronous clear.
la  in std_logic
 Active low load AC control input signal.

The documentation for this class was generated from the following file:
Generated on Wed Apr 11 09:49:19 2012 for Microprocessor 8-bit by  doxygen 1.6.3