IR Entity Reference

Inheritance diagram for IR:
behave struct MP

List of all members.



Architectures

behave Architecture

Libraries

ieee 

Packages

std_logic_1164 

Ports

clk  in std_logic
 Rising edge clock.
clr  in std_logic
 Active high asynchronous clear.
li  in std_logic
 Active low load instruction into IR.
ei  in std_logic
 Active low enable IR output.
d  in std_logic_vector ( 7 downto 0 )
 IR 8-bit input data word from W-bus.
q_w  out std_logic_vector ( 3 downto 0 )
 IR 4-bit output data word to W-bus.
q_c  out std_logic_vector ( 3 downto 0 )
 IR 4-bit output control word to Control-Sequencer block.

The documentation for this class was generated from the following file:
Generated on Wed Apr 11 09:49:20 2012 for Microprocessor 8-bit by  doxygen 1.6.3