Architectures | |
behave | Architecture |
Libraries | |
ieee | |
Packages | |
std_logic_1164 | |
Ports | |
d | in std_logic_vector ( 7 downto 0 ) |
8-bit O input from W-bus | |
q | out std_logic_vector ( 7 downto 0 ) |
8-bit O output | |
clk | in std_logic |
Rising edge clock. | |
clr | in std_logic |
Active high asynchronous clear. | |
lo | in std_logic |
Active low load O content into output. |