CU Entity Reference
List of all members.
Architectures |
fsm | Architecture |
Libraries |
ieee | |
Packages |
std_logic_1164 | |
std_logic_arith | |
std_logic_unsigned | |
Ports |
ADD | in |
| Add instruction.
|
CLK | in |
| Positive edge trigger clock.
|
CLR | in |
| Active high asynchronous clear.
|
LDA | in |
| Load Accumulator instruction.
|
O | in |
| Out instruction.
|
SUB | in |
| Sub instruction.
|
CON | out ( 11 downto 0 ) |
| 12-bit control word forming control bus ~ ~ ~ ~ ~ ~ ~ ~ CpEpLmCE LiEiLaEa SuEuLbLo
|
The documentation for this class was generated from the following file: