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ClockDivider Entity Reference
Inheritance diagram for ClockDivider:
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Collaboration diagram for ClockDivider:
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List of all members.
Architectures
Behavioral
Architecture
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IEEE
Packages
STD_LOGIC_1164
STD_LOGIC_ARITH
STD_LOGIC_UNSIGNED
Ports
CLK_Divider_CLR
in
std_logic
CLK_Divider_CLK
in
std_logic
CLK_Divider_Out
out
std_logic
The documentation for this class was generated from the following file:
testFPGA/ClockDivider.vhd
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Generated on Tue Apr 10 20:26:43 2012 for Microprocessor 8-bit by
1.6.3