Architectures | |
behave | Architecture |
Libraries | |
ieee | |
Packages | |
std_logic_1164 | |
std_logic_arith | |
std_logic_unsigned | |
Ports | |
CLK | in std_logic |
Rising edge clock. | |
CLR | in std_logic |
Active high asynchronous clear. | |
Lm | in std_logic |
Active low load MAR. | |
D | in std_logic_vector ( 3 downto 0 ) |
MAR 4-bit address input. | |
Q | out std_logic_vector ( 3 downto 0 ) |
MAR 4-bit address output. |