AC Entity Reference
List of all members.
Architectures |
behave | Architecture |
Libraries |
ieee | |
Packages |
std_logic_1164 | |
std_logic_arith | |
std_logic_unsigned | |
Ports |
d | in ( 7 downto 0 ) |
| 8-bit input data to AC from W-bus
|
q_alu | out ( 7 downto 0 ) |
| 8-bit output data to AC from W-bus
|
q_data | out ( 7 downto 0 ) |
| 8-bit output data to Adder-Subtractor block
|
clk | in |
| Rising edge clock.
|
ea | in |
| Active high enable AC control input signal.
|
clr | in |
| Active high asynchronous clear.
|
la | in |
| Active low load AC control input signal.
|
The documentation for this class was generated from the following file: