Single 14 Segment Display Driver with Limited ASCII Decoder  0.1
Ports | Libraries | Use Clauses
display_driver_w_decoder Entity Reference

Top entity of the display driver. More...

Inheritance diagram for display_driver_w_decoder:
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Collaboration diagram for display_driver_w_decoder:
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Entities

display_driver_w_decoder_arch  architecture
 Architecture definition of the display_driver_w_decoder. More...
 

Libraries

ieee 

Use Clauses

std_logic_1164 
numeric_std 

Ports

clk   in std_logic
 input clock, xx MHz.
reset   in std_logic
 active high
ascii_in   in std_logic_vector ( 7 downto 0 )
 input ASCII code to display
wr_en   in std_logic
 active high write enable to store the ASCII code in a register
disp_data_q   out std_logic_vector ( 14 downto 0 )
disp_sel   out std_logic

Detailed Description

Top entity of the display driver.

Top entity of the decoder architecture. Module description also goes here.

Member Data Documentation

◆ disp_data_q

disp_data_q out std_logic_vector ( 14 downto 0 )
Port

Typically the data fed to display (single or multiple) is provided for single display at a time. If multiple displays are required disp_sel signal must be provided (according typical dynamic display indication).

Display Segment Bit Mapping

Bit Number 14131211109876543210
Display Segmentdpmlkjihg2g1fedcba

Note that there is no standard way to name the segments. Current data bits correspondt to display segments according this picture: https://www.maximintegrated.com/en/images/appnotes/3211/3211Fig02.gif

◆ disp_sel

disp_sel out std_logic
Port

If more displays needs to be fed change disp_sel to vector with length equal to number of displays. Use principles of the standard dynamic indication: provide data then enable the displays sequentially. If brightness control is desired just AND the selector and the PWM controller output.


The documentation for this class was generated from the following file: