#
# Copyright 2013-2014, Sinclair R.F., Inc.
#
# Test bench for big_outport peripheral.
#

ARCHITECTURE    core/9x8 Verilog
INSTRUCTION     128
DATA_STACK      32
RETURN_STACK    16

PORTCOMMENT     very big outport signal
PERIPHERAL      big_outport     outport=O_VB    \
                                outsignal=o_vb  \
                                width=26
OUTPORT         strobe  o_wr_26bit      O_WR_26BIT
OUTPORT         strobe  o_wr_18bit      O_WR_18BIT

PORTCOMMENT     minimal composite signal
PERIPHERAL      big_outport     outport=O_MIN   \
                                outsignal=o_min \
                                width=9
OUTPORT         strobe  o_wr_9bit       O_WR_9BIT

PORTCOMMENT termination signal
OUTPORT 1-bit o_done O_DONE

ASSEMBLY tb_big_outport.s