NAME |
DIR |
[MSB:LSB] |
SIG |
ATTRS |
fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn_pin |
O |
1 |
fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn |
|
fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin |
O |
2:0 |
fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk |
|
fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin |
O |
2:0 |
fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn |
|
fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin |
O |
7:0 |
fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM |
|
fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn_pin |
O |
1 |
fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn |
|
fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn_pin |
O |
1 |
fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn |
|
fpga_0_DDR_CLK_FB_OUT |
O |
1 |
ddr_clk_feedback_out_s |
|
fpga_0_RS232_Uart_1_TX_pin |
O |
1 |
fpga_0_RS232_Uart_1_TX |
|
fpga_0_SysACE_CompactFlash_SysACE_CEN_pin |
O |
1 |
fpga_0_SysACE_CompactFlash_SysACE_CEN |
|
fpga_0_SysACE_CompactFlash_SysACE_MPA_pin |
O |
6:0 |
fpga_0_SysACE_CompactFlash_SysACE_MPA |
|
fpga_0_SysACE_CompactFlash_SysACE_OEN_pin |
O |
1 |
fpga_0_SysACE_CompactFlash_SysACE_OEN |
|
fpga_0_SysACE_CompactFlash_SysACE_WEN_pin |
O |
1 |
fpga_0_SysACE_CompactFlash_SysACE_WEN |
|
|