TABLE OF CONTENTS

Overview
System Pinout
Processors
   microblaze_0
          memory map
   microblaze_2
          memory map
Debuggers
   debug_module
Busses
   dlmb0
   dlmb2
   fsl0m
   fsl0s
   fsl2m
   fsl2s
   ilmb0
   ilmb2
   mb_opb
Memory
   lmb_bram0
   lmb_bram2
Memory Controllers
   dlmb_cntlr0
   dlmb_cntlr2
   ilmb_cntlr0
   ilmb_cntlr2
Peripherals
   DDR_256MB_32MX64_rank1_row13_col10_cl2_5
   RS232_Uart_1
   SysACE_CompactFlash
   clk90_inv
   dcm_0
   dcm_1
   ddr_clk90_inv
   fifo02
   fifo20
   sysclk_inv
Timing Information



Overview TOC


Overview
Generated on Sun Oct 22 11:19:35 2006
Source D:/mpdma/system.xmp
EDK Version 7.1.2
FPGA Family virtex2p
Device xc2vp30ff896-7
# IP Instantiated 28
# Processors 2
# Busses 9



System Pinout TOC


SYSTEM PINOUT
These are the system ports listed in the MHS file.
ATTRS Key
CLK  are clock ports 
INTR  are interrupt ports 
BUF or REG  are ports that instantiate or infer IOB primitives: 
NAME DIR [MSB:LSB] SIG ATTRS
fpga_0_DDR_CLK_FB I 1 ddr_feedback_s
fpga_0_RS232_Uart_1_RX_pin I 1 fpga_0_RS232_Uart_1_RX
fpga_0_SysACE_CompactFlash_SysACE_CLK_pin I 1 fpga_0_SysACE_CompactFlash_SysACE_CLK
fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin I 1 fpga_0_SysACE_CompactFlash_SysACE_MPIRQ
sys_clk_pin I 1 dcm_clk_s
sys_rst_pin I 1 sys_rst_s
fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin IO 7:0 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS
fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin IO 63:0 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ
fpga_0_SysACE_CompactFlash_SysACE_MPD_pin IO 15:0 fpga_0_SysACE_CompactFlash_SysACE_MPD
fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin O 12:0 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr
fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr_pin O 1:0 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr
fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn_pin O 1 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn
fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE_pin O 1 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE
 
NAME DIR [MSB:LSB] SIG ATTRS
fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn_pin O 1 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn
fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin O 2:0 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk
fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin O 2:0 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn
fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin O 7:0 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM
fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn_pin O 1 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn
fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn_pin O 1 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn
fpga_0_DDR_CLK_FB_OUT O 1 ddr_clk_feedback_out_s
fpga_0_RS232_Uart_1_TX_pin O 1 fpga_0_RS232_Uart_1_TX
fpga_0_SysACE_CompactFlash_SysACE_CEN_pin O 1 fpga_0_SysACE_CompactFlash_SysACE_CEN
fpga_0_SysACE_CompactFlash_SysACE_MPA_pin O 6:0 fpga_0_SysACE_CompactFlash_SysACE_MPA
fpga_0_SysACE_CompactFlash_SysACE_OEN_pin O 1 fpga_0_SysACE_CompactFlash_SysACE_OEN
fpga_0_SysACE_CompactFlash_SysACE_WEN_pin O 1 fpga_0_SysACE_CompactFlash_SysACE_WEN
 



Processors TOC

microblaze_0


microblaze_0 IP Image
PINOUT
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [MSB:LSB] SIGNAL
1 CLK I 1 sys_clk_s
2 DBG_CAPTURE I 1 DBG_CAPTURE_s
3 DBG_CLK I 1 DBG_CLK_s
4 DBG_REG_EN I 4:0 DBG_REG_EN_s
5 DBG_TDI I 1 DBG_TDI_s
6 DBG_UPDATE I 1 DBG_UPDATE_s
7 DBG_TDO O 1 DBG_TDO_s
Bus Interfaces
TYPE NAME STD BUS P2P
MASTER DLMB LMB dlmb0 dlmb_cntlr0
MASTER ILMB LMB ilmb0 ilmb_cntlr0
MASTER DOPB OPB mb_opb NA
MASTER IOPB OPB mb_opb NA
MASTER MFSL0 FSL fsl0m fifo02
SLAVE SFSL0 FSL fsl0s fifo20


General
IP Core microblaze
Version 4.00.a
Driver API
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_ADDR_TAG_BITS 0
C_ALLOW_DCACHE_WR 1
C_ALLOW_ICACHE_WR 1
C_CACHE_BYTE_SIZE 8192
C_DCACHE_ADDR_TAG 0
C_DCACHE_BASEADDR 0x00000000
C_DCACHE_BYTE_SIZE 8192
C_DCACHE_HIGHADDR 0x3FFFFFFF
C_DCACHE_USE_FSL 0
C_DEBUG_ENABLED 1
C_DIV_ZERO_EXCEPTION 0
C_DOPB_BUS_EXCEPTION 0
C_D_LMB 1
C_D_OPB 1
C_EDGE_IS_POSITIVE 1
C_FAMILY virtex2p
C_FPU_EXCEPTION 0
C_FSL_DATA_SIZE 32
C_FSL_LINKS 1
C_ICACHE_BASEADDR 0x00000000
 
Name Value
C_ICACHE_HIGHADDR 0x3FFFFFFF
C_ICACHE_USE_FSL 0
C_ILL_OPCODE_EXCEPTION 0
C_INSTANCE microblaze_0
C_INTERRUPT_IS_EDGE 0
C_IOPB_BUS_EXCEPTION 0
C_I_LMB 1
C_I_OPB 1
C_NUMBER_OF_PC_BRK 2
C_NUMBER_OF_RD_ADDR_BRK 1
C_NUMBER_OF_WR_ADDR_BRK 1
C_UNALIGNED_EXCEPTIONS 0
C_USE_BARREL 0
C_USE_DCACHE 0
C_USE_DIV 0
C_USE_FPU 0
C_USE_HW_MUL 1
C_USE_ICACHE 0
C_USE_MSR_INSTR 0
C_USE_PCMP_INSTR 0
MEMORY MAP
D=DATA ADDRESSABLE    I=INSTRUCTION ADDRESSABLE
D I BASE HIGH MODULE
  0x00000000 0x0000FFFF dlmb_cntlr0
  0x00000000 0x0000FFFF ilmb_cntlr0
0x30000000 0x3FFFFFFF DDR_256MB_32MX64_rank1_row13_col10_cl2_5
0x40600000 0x4060FFFF RS232_Uart_1
0x41400000 0x4140FFFF debug_module
0x41800000 0x4180FFFF SysACE_CompactFlash
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 948 13696 6
Slice Flip Flops 809 27392 2
4 input LUTs 1311 27392 4
bonded IOBs 1300 556 233
MULT18X18s 3 136 2


microblaze_2


microblaze_2 IP Image
PINOUT
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [MSB:LSB] SIGNAL
1 CLK I 1 sys_clk_s
Bus Interfaces
TYPE NAME STD BUS P2P
MASTER DLMB LMB dlmb2 dlmb_cntlr2
MASTER ILMB LMB ilmb2 ilmb_cntlr2
MASTER DOPB OPB mb_opb NA
MASTER IOPB OPB mb_opb NA
MASTER MFSL0 FSL fsl2m fifo20
SLAVE SFSL0 FSL fsl2s fifo02


General
IP Core microblaze
Version 4.00.a
Driver API
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_ADDR_TAG_BITS 0
C_ALLOW_DCACHE_WR 1
C_ALLOW_ICACHE_WR 1
C_CACHE_BYTE_SIZE 8192
C_DCACHE_ADDR_TAG 0
C_DCACHE_BASEADDR 0x00000000
C_DCACHE_BYTE_SIZE 8192
C_DCACHE_HIGHADDR 0x3FFFFFFF
C_DCACHE_USE_FSL 0
C_DEBUG_ENABLED 1
C_DIV_ZERO_EXCEPTION 0
C_DOPB_BUS_EXCEPTION 0
C_D_LMB 1
C_D_OPB 1
C_EDGE_IS_POSITIVE 1
C_FAMILY virtex2p
C_FPU_EXCEPTION 0
C_FSL_DATA_SIZE 32
C_FSL_LINKS 1
C_ICACHE_BASEADDR 0x00000000
 
Name Value
C_ICACHE_HIGHADDR 0x3FFFFFFF
C_ICACHE_USE_FSL 0
C_ILL_OPCODE_EXCEPTION 0
C_INSTANCE microblaze_2
C_INTERRUPT_IS_EDGE 0
C_IOPB_BUS_EXCEPTION 0
C_I_LMB 1
C_I_OPB 1
C_NUMBER_OF_PC_BRK 2
C_NUMBER_OF_RD_ADDR_BRK 1
C_NUMBER_OF_WR_ADDR_BRK 1
C_UNALIGNED_EXCEPTIONS 0
C_USE_BARREL 0
C_USE_DCACHE 0
C_USE_DIV 0
C_USE_FPU 0
C_USE_HW_MUL 1
C_USE_ICACHE 0
C_USE_MSR_INSTR 0
C_USE_PCMP_INSTR 0
MEMORY MAP
D=DATA ADDRESSABLE    I=INSTRUCTION ADDRESSABLE
D I BASE HIGH MODULE
  0x00000000 0x00001FFF dlmb_cntlr2
  0x00000000 0x00001FFF ilmb_cntlr2
0x30000000 0x3FFFFFFF DDR_256MB_32MX64_rank1_row13_col10_cl2_5
0x40600000 0x4060FFFF RS232_Uart_1
0x41400000 0x4140FFFF debug_module
0x41800000 0x4180FFFF SysACE_CompactFlash
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 948 13696 6
Slice Flip Flops 809 27392 2
4 input LUTs 1311 27392 4
bonded IOBs 1300 556 233
MULT18X18s 3 136 2





Debuggers TOC
debug_module


debug_module IP Image
PINOUT
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [MSB:LSB] SIGNAL
1 OPB_Clk I 1 sys_clk_s
2 DBG_TDO_0 I 1 DBG_TDO_s
3 DBG_CAPTURE_0 O 1 DBG_CAPTURE_s
4 DBG_CLK_0 O 1 DBG_CLK_s
5 DBG_REG_EN_0 O 4:0 DBG_REG_EN_s
6 DBG_TDI_0 O 1 DBG_TDI_s
7 DBG_UPDATE_0 O 1 DBG_UPDATE_s
Bus Interfaces
TYPE NAME STD BUS P2P
SLAVE SOPB OPB mb_opb NA


General
IP Core opb_mdm
Version 2.00.a
Driver API
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR 0x41400000
C_FAMILY virtex2p
C_HIGHADDR 0x4140ffff
C_MB_DBG_PORTS 1
C_OPB_AWIDTH 32
C_OPB_DWIDTH 32
C_UART_WIDTH 8
C_USE_UART 1
C_WRITE_FSL_PORTS 0
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 72 13696 0
Slice Flip Flops 79 27392 0
4 input LUTs 116 27392 0
bonded IOBs 274 556 49
GCLKs 2 16 12





Busses TOC
dlmb0


dlmb0 IP Image
PINOUT
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [MSB:LSB] SIGNAL
1 SYS_Rst I 1 sys_rst_s
2 LMB_Clk I 1 sys_clk_s
Bus Connections
TYPE NAME BIF
MASTER microblaze_0 DLMB
SLAVE dlmb_cntlr0 SLMB


General
IP Core lmb_v10
Version 1.00.a
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_EXT_RESET_HIGH 0
C_LMB_AWIDTH 32
C_LMB_DWIDTH 32
C_LMB_NUM_SLAVES 1
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 1 13696 0
Slice Flip Flops 1 27392 0
4 input LUTs 1 27392 0
bonded IOBs 211 556 37


dlmb2


dlmb2 IP Image
PINOUT
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [MSB:LSB] SIGNAL
1 SYS_Rst I 1 sys_rst_s
2 LMB_Clk I 1 sys_clk_s
Bus Connections
TYPE NAME BIF
MASTER microblaze_2 DLMB
SLAVE dlmb_cntlr2 SLMB


General
IP Core lmb_v10
Version 1.00.a
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_EXT_RESET_HIGH 0
C_LMB_AWIDTH 32
C_LMB_DWIDTH 32
C_LMB_NUM_SLAVES 1
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 1 13696 0
Slice Flip Flops 1 27392 0
4 input LUTs 1 27392 0
bonded IOBs 211 556 37


fsl0m


fsl0m IP Image
PINOUT
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [MSB:LSB] SIGNAL
1 FSL_Clk I 1 sys_clk_s
2 SYS_Rst I 1 sys_rst_s
Bus Connections
TYPE NAME BIF
MASTER microblaze_0 MFSL0
SLAVE fifo02 SFSL


General
IP Core fsl_v20
Version 2.00.a
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_ASYNC_CLKS 0
C_EXT_RESET_HIGH 0
C_FSL_DEPTH 128
C_FSL_DWIDTH 32
C_IMPL_STYLE 0
C_USE_CONTROL 1
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 436 13696 3
Slice Flip Flops 31 27392 0
4 input LUTs 333 27392 1
bonded IOBs 77 556 13


fsl0s


fsl0s IP Image
PINOUT
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [MSB:LSB] SIGNAL
1 FSL_Clk I 1 sys_clk_s
2 SYS_Rst I 1 sys_rst_s
Bus Connections
TYPE NAME BIF
MASTER fifo20 MFSL
SLAVE microblaze_0 SFSL0


General
IP Core fsl_v20
Version 2.00.a
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_ASYNC_CLKS 0
C_EXT_RESET_HIGH 0
C_FSL_DEPTH 128
C_FSL_DWIDTH 32
C_IMPL_STYLE 0
C_USE_CONTROL 1
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 436 13696 3
Slice Flip Flops 31 27392 0
4 input LUTs 333 27392 1
bonded IOBs 77 556 13


fsl2m


fsl2m IP Image
PINOUT
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [MSB:LSB] SIGNAL
1 FSL_Clk I 1 sys_clk_s
2 SYS_Rst I 1 sys_rst_s
Bus Connections
TYPE NAME BIF
MASTER microblaze_2 MFSL0
SLAVE fifo20 SFSL


General
IP Core fsl_v20
Version 2.00.a
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_ASYNC_CLKS 0
C_EXT_RESET_HIGH 0
C_FSL_DEPTH 128
C_FSL_DWIDTH 32
C_IMPL_STYLE 0
C_USE_CONTROL 1
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 436 13696 3
Slice Flip Flops 31 27392 0
4 input LUTs 333 27392 1
bonded IOBs 77 556 13


fsl2s


fsl2s IP Image
PINOUT
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [MSB:LSB] SIGNAL
1 FSL_Clk I 1 sys_clk_s
2 SYS_Rst I 1 sys_rst_s
Bus Connections
TYPE NAME BIF
MASTER fifo02 MFSL
SLAVE microblaze_2 SFSL0


General
IP Core fsl_v20
Version 2.00.a
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_ASYNC_CLKS 0
C_EXT_RESET_HIGH 0
C_FSL_DEPTH 128
C_FSL_DWIDTH 32
C_IMPL_STYLE 0
C_USE_CONTROL 1
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 436 13696 3
Slice Flip Flops 31 27392 0
4 input LUTs 333 27392 1
bonded IOBs 77 556 13


ilmb0


ilmb0 IP Image
PINOUT
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [MSB:LSB] SIGNAL
1 SYS_Rst I 1 sys_rst_s
2 LMB_Clk I 1 sys_clk_s
Bus Connections
TYPE NAME BIF
MASTER microblaze_0 ILMB
SLAVE ilmb_cntlr0 SLMB


General
IP Core lmb_v10
Version 1.00.a
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_EXT_RESET_HIGH 0
C_LMB_AWIDTH 32
C_LMB_DWIDTH 32
C_LMB_NUM_SLAVES 1
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 1 13696 0
Slice Flip Flops 1 27392 0
4 input LUTs 1 27392 0
bonded IOBs 211 556 37


ilmb2


ilmb2 IP Image
PINOUT
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [MSB:LSB] SIGNAL
1 SYS_Rst I 1 sys_rst_s
2 LMB_Clk I 1 sys_clk_s
Bus Connections
TYPE NAME BIF
MASTER microblaze_2 ILMB
SLAVE ilmb_cntlr2 SLMB


General
IP Core lmb_v10
Version 1.00.a
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_EXT_RESET_HIGH 0
C_LMB_AWIDTH 32
C_LMB_DWIDTH 32
C_LMB_NUM_SLAVES 1
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 1 13696 0
Slice Flip Flops 1 27392 0
4 input LUTs 1 27392 0
bonded IOBs 211 556 37


mb_opb


mb_opb IP Image
PINOUT
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [MSB:LSB] SIGNAL
1 SYS_Rst I 1 sys_rst_s
2 OPB_Clk I 1 sys_clk_s
Bus Connections
TYPE NAME BIF
MASTER microblaze_0 DOPB
MASTER microblaze_0 IOPB
MASTER microblaze_2 DOPB
MASTER microblaze_2 IOPB
SLAVE debug_module SOPB
SLAVE RS232_Uart_1 SOPB
SLAVE SysACE_CompactFlash SOPB
SLAVE DDR_256MB_32MX64_rank1_row13_col10_cl2_5 SOPB


General
IP Core opb_v20
Version 1.10.c
Driver API
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR 0xFFFFFFFF
C_DEV_BLK_ID 0
C_DEV_MIR_ENABLE 0
C_DYNAM_PRIORITY 0
C_EXT_RESET_HIGH 0
C_HIGHADDR 0x00000000
C_NUM_MASTERS 4
 
Name Value
C_NUM_SLAVES 4
C_OPB_AWIDTH 32
C_OPB_DWIDTH 32
C_PARK 0
C_PROC_INTRFCE 0
C_REG_GRANTS 1
C_USE_LUT_OR 1
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 111 13696 0
Slice Flip Flops 15 27392 0
4 input LUTs 180 27392 0
bonded IOBs 650 556 116





Memory TOC
lmb_bram0


lmb_bram0 IP Image
PINOUT
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [MSB:LSB] SIGNAL
Bus Interfaces
TYPE NAME STD BUS P2P
TRANSPARENT PORTA NA ilmb_port0 ilmb_cntlr0
TRANSPARENT PORTB NA dlmb_port0 dlmb_cntlr0


General
IP Core bram_block
Version 1.00.a
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex2p
C_MEMSIZE 65536
C_NUM_WE 4
C_PORT_AWIDTH 32
C_PORT_DWIDTH 32
Post Synthesis Device Utilization
Resource Type Used Available Percent
bonded IOBs 206 556 37
BRAMs 32 136 23


lmb_bram2


lmb_bram2 IP Image
PINOUT
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [MSB:LSB] SIGNAL
Bus Interfaces
TYPE NAME STD BUS P2P
TRANSPARENT PORTA NA ilmb_port2 ilmb_cntlr2
TRANSPARENT PORTB NA dlmb_port2 dlmb_cntlr2


General
IP Core bram_block
Version 1.00.a
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex2p
C_MEMSIZE 8192
C_NUM_WE 4
C_PORT_AWIDTH 32
C_PORT_DWIDTH 32
Post Synthesis Device Utilization
Resource Type Used Available Percent
bonded IOBs 206 556 37
BRAMs 4 136 2





Memory Controllers TOC
dlmb_cntlr0


dlmb_cntlr0 IP Image
PINOUT
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [MSB:LSB] SIGNAL
Bus Interfaces
TYPE NAME STD BUS P2P
SLAVE SLMB LMB dlmb0 microblaze_0
TRANSPARENT BRAM_PORT NA dlmb_port0 lmb_bram0


General
IP Core lmb_bram_if_cntlr
Version 1.00.b
Driver API
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR 0x00000000
C_HIGHADDR 0x0000ffff
C_LMB_AWIDTH 32
C_LMB_DWIDTH 32
C_MASK 0x10c00000
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 3 13696 0
Slice Flip Flops 1 27392 0
4 input LUTs 5 27392 0
bonded IOBs 209 556 37


dlmb_cntlr2


dlmb_cntlr2 IP Image
PINOUT
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [MSB:LSB] SIGNAL
Bus Interfaces
TYPE NAME STD BUS P2P
SLAVE SLMB LMB dlmb2 microblaze_2
TRANSPARENT BRAM_PORT NA dlmb_port2 lmb_bram2


General
IP Core lmb_bram_if_cntlr
Version 1.00.b
Driver API
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR 0x00000000
C_HIGHADDR 0x00001fff
C_LMB_AWIDTH 32
C_LMB_DWIDTH 32
C_MASK 0x10c00000
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 3 13696 0
Slice Flip Flops 1 27392 0
4 input LUTs 5 27392 0
bonded IOBs 209 556 37


ilmb_cntlr0


ilmb_cntlr0 IP Image
PINOUT
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [MSB:LSB] SIGNAL
Bus Interfaces
TYPE NAME STD BUS P2P
SLAVE SLMB LMB ilmb0 microblaze_0
TRANSPARENT BRAM_PORT NA ilmb_port0 lmb_bram0


General
IP Core lmb_bram_if_cntlr
Version 1.00.b
Driver API
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR 0x00000000
C_HIGHADDR 0x0000ffff
C_LMB_AWIDTH 32
C_LMB_DWIDTH 32
C_MASK 0x10c00000
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 3 13696 0
Slice Flip Flops 1 27392 0
4 input LUTs 5 27392 0
bonded IOBs 209 556 37


ilmb_cntlr2


ilmb_cntlr2 IP Image
PINOUT
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [MSB:LSB] SIGNAL
Bus Interfaces
TYPE NAME STD BUS P2P
SLAVE SLMB LMB ilmb2 microblaze_2
TRANSPARENT BRAM_PORT NA ilmb_port2 lmb_bram2


General
IP Core lmb_bram_if_cntlr
Version 1.00.b
Driver API
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR 0x00000000
C_HIGHADDR 0x00001fff
C_LMB_AWIDTH 32
C_LMB_DWIDTH 32
C_MASK 0x10c00000
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 3 13696 0
Slice Flip Flops 1 27392 0
4 input LUTs 5 27392 0
bonded IOBs 209 556 37





Peripherals TOC
DDR_256MB_32MX64_rank1_row13_col10_cl2_5


DDR_256MB_32MX64_rank1_row13_col10_cl2_5 IP Image
PINOUT
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [MSB:LSB] SIGNAL
1 OPB_Clk I 1 sys_clk_s
2 Device_Clk90_in I 1 clk_90_s
3 Device_Clk90_in_n I 1 clk_90_n_s
4 Device_Clk I 1 sys_clk_s
5 Device_Clk_n I 1 sys_clk_n_s
6 DDR_Clk90_in I 1 ddr_clk_90_s
7 DDR_Clk90_in_n I 1 ddr_clk_90_n_s
8 DDR_DQS IO 7:0 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS
9 DDR_DQ IO 63:0 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ
10 DDR_Addr O 12:0 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr
11 DDR_BankAddr O 1:0 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr
12 DDR_CASn O 1 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn
13 DDR_CKE O 1 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE
14 DDR_CSn O 1 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn
15 DDR_RASn O 1 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn
16 DDR_WEn O 1 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn
17 DDR_DM O 7:0 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM
18 DDR_Clk O 3:0 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk & ddr_clk_feedback_out_s
19 DDR_Clkn O 3:0 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn & 0b0
Bus Interfaces
TYPE NAME STD BUS P2P
SLAVE SOPB OPB mb_opb NA


General
IP Core opb_ddr
Version 2.00.b
Driver API
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_DDR_ASYNC_SUPPORT 0
C_DDR_AWIDTH 13
C_DDR_BANK_AWIDTH 2
C_DDR_CAS_LAT 2
C_DDR_COL_AWIDTH 10
C_DDR_DWIDTH 64
C_DDR_TMRD 20000
C_DDR_TRAS 60000
C_DDR_TRC 90000
C_DDR_TRCD 30000
C_DDR_TREFC 70300000
C_DDR_TREFI 7800000
C_DDR_TRFC 100000
C_DDR_TRP 30000
C_DDR_TRRD 20000
C_DDR_TWR 20000
C_DDR_TWTR 1
C_EXTRA_TSU 0
 
Name Value
C_FAMILY virtex2p
C_INCLUDE_BURST_SUPPORT 0
C_MEM0_BASEADDR 0x30000000
C_MEM0_HIGHADDR 0x3fffffff
C_MEM1_BASEADDR 0xffffffff
C_MEM1_HIGHADDR 0x00000000
C_MEM2_BASEADDR 0xffffffff
C_MEM2_HIGHADDR 0x00000000
C_MEM3_BASEADDR 0xffffffff
C_MEM3_HIGHADDR 0x00000000
C_NUM_BANKS_MEM 1
C_NUM_CLK_PAIRS 4
C_OPB_AWIDTH 32
C_OPB_CLK_PERIOD_PS 10000
C_OPB_DWIDTH 32
C_REG_DIMM 0
C_SIM_INIT_TIME_PS 200000000
 
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 970 13696 7
Slice Flip Flops 990 27392 3
4 input LUTs 641 27392 2
bonded IOBs 368 556 66


RS232_Uart_1


RS232_Uart_1 IP Image
PINOUT
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [MSB:LSB] SIGNAL
1 OPB_Clk I 1 sys_clk_s
2 RX I 1 fpga_0_RS232_Uart_1_RX
3 TX O 1 fpga_0_RS232_Uart_1_TX
Bus Interfaces
TYPE NAME STD BUS P2P
SLAVE SOPB OPB mb_opb NA


General
IP Core opb_uartlite
Version 1.00.b
Driver API
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR 0x40600000
C_BAUDRATE 9600
C_CLK_FREQ 100000000
C_DATA_BITS 8
C_HIGHADDR 0x4060ffff
C_ODD_PARITY 0
C_OPB_AWIDTH 32
C_OPB_DWIDTH 32
C_USE_PARITY 0
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 54 13696 0
Slice Flip Flops 64 27392 0
4 input LUTs 88 27392 0
bonded IOBs 112 556 20


SysACE_CompactFlash


SysACE_CompactFlash IP Image
PINOUT
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [MSB:LSB] SIGNAL
1 OPB_Clk I 1 sys_clk_s
2 SysACE_CLK I 1 fpga_0_SysACE_CompactFlash_SysACE_CLK
3 SysACE_MPIRQ I 1 fpga_0_SysACE_CompactFlash_SysACE_MPIRQ
4 SysACE_MPD IO 15:0 fpga_0_SysACE_CompactFlash_SysACE_MPD
5 SysACE_MPA O 6:0 fpga_0_SysACE_CompactFlash_SysACE_MPA
6 SysACE_CEN O 1 fpga_0_SysACE_CompactFlash_SysACE_CEN
7 SysACE_OEN O 1 fpga_0_SysACE_CompactFlash_SysACE_OEN
8 SysACE_WEN O 1 fpga_0_SysACE_CompactFlash_SysACE_WEN
Bus Interfaces
TYPE NAME STD BUS P2P
SLAVE SOPB OPB mb_opb NA


General
IP Core opb_sysace
Version 1.00.c
Driver API
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR 0x41800000
C_HIGHADDR 0x4180ffff
C_MEM_WIDTH 16
C_OPB_AWIDTH 32
C_OPB_DWIDTH 32
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 149 13696 1
Slice Flip Flops 258 27392 0
4 input LUTs 71 27392 0
bonded IOBs 170 556 30


clk90_inv


clk90_inv IP Image
PINOUT
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [MSB:LSB] SIGNAL
1 Op1 I 1 clk_90_s
2 Res O 1 clk_90_n_s


General
IP Core util_vector_logic
Version 1.00.a
Driver API
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_OPERATION not
C_SIZE 1
Post Synthesis Device Utilization
Resource Type Used Available Percent
bonded IOBs 3 556 0


dcm_0


dcm_0 IP Image
PINOUT
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [MSB:LSB] SIGNAL
1 CLKIN I 1 dcm_clk_s
2 CLKFB I 1 sys_clk_s
3 RST I 1 net_gnd
4 CLK0 O 1 sys_clk_s
5 CLK90 O 1 clk_90_s
6 LOCKED O 1 dcm_0_lock


General
IP Core dcm_module
Version 1.00.a
Driver API
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_CLK0_BUF TRUE
C_CLK180_BUF FALSE
C_CLK270_BUF FALSE
C_CLK2X180_BUF FALSE
C_CLK2X_BUF FALSE
C_CLK90_BUF TRUE
C_CLKDV_BUF FALSE
C_CLKDV_DIVIDE 2.0
C_CLKFB_BUF FALSE
C_CLKFX180_BUF FALSE
C_CLKFX_BUF FALSE
C_CLKFX_DIVIDE 1
C_CLKFX_MULTIPLY 4
C_CLKIN_BUF FALSE
 
Name Value
C_CLKIN_DIVIDE_BY_2 FALSE
C_CLKIN_PERIOD 10.000000
C_CLKOUT_PHASE_SHIFT NONE
C_CLK_FEEDBACK 1X
C_DESKEW_ADJUST SYSTEM_SYNCHRONOUS
C_DFS_FREQUENCY_MODE LOW
C_DLL_FREQUENCY_MODE LOW
C_DSS_MODE NONE
C_DUTY_CYCLE_CORRECTION TRUE
C_EXT_RESET_HIGH 1
C_FAMILY virtex2p
C_PHASE_SHIFT 0
C_STARTUP_WAIT FALSE
 
Post Synthesis Device Utilization
Resource Type Used Available Percent
bonded IOBs 26 556 4
GCLKs 2 16 12
DCM_ADVs 1 8 12


dcm_1


dcm_1 IP Image
PINOUT
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [MSB:LSB] SIGNAL
1 CLKIN I 1 ddr_feedback_s
2 CLKFB I 1 dcm_1_FB
3 RST I 1 dcm_0_lock
4 CLK90 O 1 ddr_clk_90_s
5 CLK0 O 1 dcm_1_FB
6 LOCKED O 1 dcm_1_lock


General
IP Core dcm_module
Version 1.00.a
Driver API
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_CLK0_BUF TRUE
C_CLK180_BUF FALSE
C_CLK270_BUF FALSE
C_CLK2X180_BUF FALSE
C_CLK2X_BUF FALSE
C_CLK90_BUF TRUE
C_CLKDV_BUF FALSE
C_CLKDV_DIVIDE 2.0
C_CLKFB_BUF FALSE
C_CLKFX180_BUF FALSE
C_CLKFX_BUF FALSE
C_CLKFX_DIVIDE 1
C_CLKFX_MULTIPLY 4
C_CLKIN_BUF FALSE
 
Name Value
C_CLKIN_DIVIDE_BY_2 FALSE
C_CLKIN_PERIOD 10.000000
C_CLKOUT_PHASE_SHIFT FIXED
C_CLK_FEEDBACK 1X
C_DESKEW_ADJUST SYSTEM_SYNCHRONOUS
C_DFS_FREQUENCY_MODE LOW
C_DLL_FREQUENCY_MODE LOW
C_DSS_MODE NONE
C_DUTY_CYCLE_CORRECTION TRUE
C_EXT_RESET_HIGH 0
C_FAMILY virtex2p
C_PHASE_SHIFT 60
C_STARTUP_WAIT FALSE
 
Post Synthesis Device Utilization
Resource Type Used Available Percent
bonded IOBs 26 556 4
GCLKs 2 16 12
DCM_ADVs 1 8 12


ddr_clk90_inv


ddr_clk90_inv IP Image
PINOUT
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [MSB:LSB] SIGNAL
1 Op1 I 1 ddr_clk_90_s
2 Res O 1 ddr_clk_90_n_s


General
IP Core util_vector_logic
Version 1.00.a
Driver API
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_OPERATION not
C_SIZE 1
Post Synthesis Device Utilization
Resource Type Used Available Percent
bonded IOBs 3 556 0


fifo02


fifo02 IP Image
PINOUT
The ports listed here are only those connected in the MHS file.
# NAME DIR [MSB:LSB] SIGNAL
Bus Interfaces
TYPE NAME STD BUS P2P
MASTER MFSL FSL fsl2s microblaze_2
SLAVE SFSL FSL fsl0m microblaze_0


General
IP Core fifo_link
Version 1.00.a
Driver API
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 1 13696 0
4 input LUTs 1 27392 0
bonded IOBs 74 556 13


fifo20


fifo20 IP Image
PINOUT
The ports listed here are only those connected in the MHS file.
# NAME DIR [MSB:LSB] SIGNAL
Bus Interfaces
TYPE NAME STD BUS P2P
MASTER MFSL FSL fsl0s microblaze_0
SLAVE SFSL FSL fsl2m microblaze_2


General
IP Core fifo_link
Version 1.00.a
Driver API
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 1 13696 0
4 input LUTs 1 27392 0
bonded IOBs 74 556 13


sysclk_inv


sysclk_inv IP Image
PINOUT
The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports.
# NAME DIR [MSB:LSB] SIGNAL
1 Op1 I 1 sys_clk_s
2 Res O 1 sys_clk_n_s


General
IP Core util_vector_logic
Version 1.00.a
Driver API
Parameters
These are parameters set for this module. Refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_OPERATION not
C_SIZE 1
Post Synthesis Device Utilization
Resource Type Used Available Percent
bonded IOBs 3 556 0





Timing Information TOC


Post Synthesis Clock Limits
These are the post synthesis clock frequencies. The critical frequencies are marked with green.
The values reported here are post synthesis estimates calculated for each individual module. These values will change after place and route is performed on the entire system.
MODULE CLK Port MAX FREQ
microblaze_0 CLK 149.982MHz
microblaze_0 DBG_CLK 149.982MHz
microblaze_2 CLK 149.982MHz
microblaze_2 DBG_CLK 149.982MHz
DDR_256MB_32MX64_rank1_row13_col10_cl2_5 Device_Clk90_in 176.229MHz
DDR_256MB_32MX64_rank1_row13_col10_cl2_5 Device_Clk90_in_n 176.229MHz
DDR_256MB_32MX64_rank1_row13_col10_cl2_5 OPB_Clk 176.229MHz
DDR_256MB_32MX64_rank1_row13_col10_cl2_5 DDR_Clk90_in 176.229MHz
DDR_256MB_32MX64_rank1_row13_col10_cl2_5 DDR_Clk90_in_n 176.229MHz
DDR_256MB_32MX64_rank1_row13_col10_cl2_5 Device_Clk 176.229MHz
DDR_256MB_32MX64_rank1_row13_col10_cl2_5 Device_Clk_n 176.229MHz
RS232_Uart_1 OPB_Clk 236.770MHz
debug_module debug_module/BSCAN_VIRTEX_I:DRCK2 239.223MHz
debug_module OPB_Clk 239.223MHz
debug_module debug_module/BSCAN_VIRTEX_I:UPDATE 239.223MHz
fsl0m FSL_Clk 243.318MHz
fsl0s FSL_Clk 243.318MHz
fsl2m FSL_Clk 243.318MHz
fsl2s FSL_Clk 243.318MHz
mb_opb OPB_Clk 269.633MHz
SysACE_CompactFlash SysACE_CLK 282.414MHz
SysACE_CompactFlash OPB_Clk 282.414MHz
ilmb0 LMB_Clk 306.796MHz
dlmb0 LMB_Clk 306.796MHz
ilmb2 LMB_Clk 306.796MHz
dlmb2 LMB_Clk 306.796MHz


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