Main Page

From OR1K

Info OpenRISC is moving
The OpenRISC home has moved to
Please find the latest news and updates there.

The aim of the OpenRISC project is to create free and open source computing platforms.

The project strives to provide:

  • a free, open source RISC architecture with DSP features
  • a set of free, open source implementations of the architecture
  • a complete set of free, open source software development tools, libraries, operating systems and applications

Some useful hot-links:

  • OR1K emulator written in Javascript, running Linux: jor1k
  • ORCONF - The project's annual conference.

This project is now fully maintained through a Wiki (the Community Portal).


Name: or1k
Created: Sep 25, 2001
Updated: Mar 1, 2012
SVN Updated: Feb 24, 2011
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Processor
Language: Verilog
Development status: Stable
Additional info: ASIC proven, Design done, FPGA proven, Specification done
WishBone compliant: Yes
WishBone version: n/a
License: LGPL

Click here for the OpenRISC project details.

Active developers are welcome as maintainer of this project. The list will be updated regularly. If you think your name should be in the list, please send an email to

© copyright 1999-2017, equivalent to ORSoC AB, all rights reserved. OpenCores®, registered trademark.