Multiple Switch Debouncer in VHDL

It was detected that simulation for Altera Quartus 11.0 + Modelsim 6.6d, the simulator reports "out of range" errors in the internal counter variables (cnt_next, cnt_reg).

This error was reported by Clive Bolton.

In Xilinx toolchain this aspect was not reported as an error.

This issue was corrected by declaring the range as <b>(CNT_VAL+1)</b> for the counter registers.<br/> In Xilinx ISE13.x, the cnt_next counter output flips over to 0 at the same clock cycle that the comparison <b>cnt_reg = CNT_VAL</b>, and the counter is reset at that same clock cycle.<br/> Probably the Xilinx tools resolve the overrange by static analysis, but Modelsim 6.6d fails to do so.<br/>