Wishbone to AHB Bridge

Sorry to say so but this code: A/ Does not work. B/ Is violating almost every Verilog rule there is:

• Delays (#<..>) in code which is supposed to be FPGA proven...
• Non-blocking assignments for combinatorial code
• Incomplete sensitivity lists I have this connected to a real AHB device and it is falling over left, right and centre! (e.g. giving an ACK when there is no STB or CYC)