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Divide by 2 #1
Closed ocghost opened this issue about 20 years ago
ocghost commented about 20 years ago

In my simulations, it appears that in the case of running SCK at 1/2 the Wishbone clock rate causes problems. All cases running at 1/4 the Wishbone clock appear to function properly. Here is a summary of my simulation results with differenct SPCR control register combinations:

SPCR = 8'h50: extra SCK rising edge at end of byte SPCR = 8'h51: correct functionality SPCR = 8'h54: does not transmit first bit (only 7 SCK clocks) SPCR = 8'h55: correct functionality SPCR = 8'h58: extra SCK falling edge at end of byte SPCR = 8'h59: correct functionality SPCR = 8'h5C: does not transmit first bit (only 7 SCK clocks) SPCR = 8'h5D: correct functionality

Please let me know if you can verify these results.

Thanks, Nick

rherveille commented about 20 years ago

Bug confirmed and being examined. Bug number: spi04-01.

rherveille was assigned about 20 years ago
rherveille closed this about 20 years ago
rherveille commented about 20 years ago

Bug has been fixed. This required a major rewrite of the serial interface engine.

zxczxs commented almost 14 years ago

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