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Fixing the bug in HeaderRam.v

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Information:
Type :: BUG
Status :: OPENED
Assigned to :: nobody

Description:
-- The HeaderRam.v file has error
-- this vhdl file fixes the probloem
-- the error is in position of assignment of read_addr -- HeaderRam.vhd Khaleghian 8 Nov 2010

library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.all;
entity HeaderRam is
port (
d : in STD_LOGIC_VECTOR(7 downto 0);
waddr : in STD_LOGIC_VECTOR(9 downto 0);
raddr : in STD_LOGIC_VECTOR(9 downto 0);
we : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR(7 downto 0)
);
end HeaderRam;

architecture syn of HeaderRam is
type ram_type is array (1023 downto 0) of std_logic_vector (7 downto 0);
signal RAM : ram_type;
signal read_addr: STD_LOGIC_VECTOR(9 downto 0);
begin
q process (clk)
begin
if clk'event and clk = '1'
then
if we='1' then
RAM(conv_integer(waddr)) end if;
read_addr end if;
end process;
end syn;

Comments:

Khaleghian, Mahdi Nov 9, 2010
So, Please change these:
In compile.do file:

vcom ../design/jfifgen/HeaderRam.vhd

And In sim.do uncomment:

mem load -infile ../design/jfifgen/header.hex -format hex /JPEG_TB/U_JpegEnc/U_JFIFGen/U_Header_RAM

Thanks
Khaleghian, Mahdi Nov 9, 2010
So, Please change these:
In compile.do file:

vcom ../design/jfifgen/HeaderRam.vhd

And In sim.do uncomment:

mem load -infile ../design/jfifgen/header.hex -format hex /JPEG_TB/U_JpegEnc/U_JFIFGen/U_Header_RAM

Thanks
Khaleghian, Mahdi Nov 9, 2010
So, Please change these:
In compile.do file:

vcom ../design/jfifgen/HeaderRam.vhd

And In sim.do uncomment:

mem load -infile ../design/jfifgen/header.hex -format hex /JPEG_TB/U_JpegEnc/U_JFIFGen/U_Header_RAM

Thanks
Krepa, Michal Nov 9, 2010
Mahdi,

I will include your VHDL in project

Thanks
Michal
Khaleghian, Mahdi Nov 9, 2010
Dear Krepa, Michal,
You are right. Because my simulator can't simulate Vhdl & Verilog files simultaneously, I changed the verilog code to vhdl. I had a mistake in this change.
Any way, If someone has problem with a verilog file inside a vhld project can use vhdl version of this file.
Thanks a lot for your Jpeg encoder.
Krepa, Michal Nov 8, 2010
this is not an error...

"read_addr
In Verilog
if(a)
b d
only b

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