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Information:
Type :: BUG
Status :: OPENED
Assigned to :: nobody

Description:
Hi,
Simulation of this project in Modelsim is OK in per-synthesize mode.
But post-layout simulation results aren't as good as per-synthesize mode:
When fdct_start signal activates, after 10 clks all output signals go to unspecified sates! The fdct_ready is the first signal that goes to unspecified state.
Thanks,
Mahdi.

Comments:

huajian, ding Mar 27, 2012
Thanks for your codes,
Thanks for you,

I have already run your codes successfully on ALTERA's FPGAs.

I haven't found your YUV422 input code verison,so I change a little code in fdct.vhd,and I use a SDRAM to storage 16 line of my input image and divide them to 256*8 pixles blocks,then the FPGA needs to cache 256*8*2(8 extera lines) only,Thus, I can compress a very large image.

I am using OV5640 CMOS sensor with YUV422 output to test your codes,It can compress a image with 2560*1944 pixels in 150ms.

Here's my personal suggestings:use separate clocks in JPEG module and HOST programme interface and input BUF_FIFO.

Now I'm working on changing your code to Verilog verision.
...
Best Regards,
Zi Jian
Khaleghian, Mahdi Mar 6, 2011
Hi,
This JPEG encoder is useful, and may be more efficient, considering two notes:

1: Replacing generic VHDL codes of RAMs (HeaderRAM.v, RAM.VHD, RAMZ.VHD, SUB_RAMZ.VHD) by specific RAM module of different FPGAs (M4K of ALTERA, etc).

2: It's possible that signals with no initialization make some problems. Anyway, I found totally 17 signals with no initialization. It may help someone.

Thanks,
Mahdi.
-----------------------------------------------
BUF_FIFO.vhd(242): memrd_line '0');
BUF_FIFO.vhd(291): pix_inblk_cnt_d1 '0'
BUF_FIFO.vhd(292): read_block_cnt_d1 '0');
BUF_FIFO.vhd(314): raddr_base_line '0');
BUF_FIFO.vhd(315): raddr_tmp '0');
DCT1D.vhd(102): odv DCT1D.vhd(103): dcto 'Z');
DCT2D.VHD(117): datareadyack FDCT.vhd(261): bf_dval_m3 FDCT.vhd(262): rd_started Huffman.vhd(290): block_cnt '0');
RLE.VHD(110): divalid RLE.VHD(111): wr_cnt '0');
RLE.VHD(112): zrl_di '0');
s_divider.vhd(136): ru_s2 '0');
s_divider.vhd(137): qu_s2 '0');
Krepa, Michal Feb 23, 2011
@ assar, amin

this code has been implemented on FPGA by at least 3 different persons known to me. Typical app used was encoder plus VGA camera.

@ Khaleghian, Mahdi

about missing resets. Resets are not mandatory in FPGA and in fact it is better to not use resets when not necessary as this increases fan out and can create timing problem with very high fanouts and clock rates. Read paper http://www.xilinx.com/support/documentation/white_papers/wp272.pdf.
After programming, unitialized (in RTL) flops are set to zeros. I don't really see a point to do post layout simulation as timing analysis tool is a sign-off one. In case of timing sim/STA mismatches you should trust STA.

Michal


Khaleghian, Mahdi Feb 23, 2011
Hi,
I found following signals with no initialization,
please add these to reset sates of processes:

BUF_FIFO.vhd(242): memrd_line '0');
BUF_FIFO.vhd(312): raddr_base_line '0');
BUF_FIFO.vhd(313): raddr_tmp '0');
DCT1D.vhd(102): odv DCT1D.vhd(103): dcto 'Z');
DCT2D.VHD(117): datareadyack FDCT.vhd(261): bf_dval_m3 FDCT.vhd(262): rd_started RLE.VHD(110): divalid RLE.VHD(111): wr_cnt '0');

Mahdi,
assar, amin Feb 22, 2011
I think this code has not implemented on FPGA yet, and it just works in behavioral simulation. So, Could anyone tell me about implementation of this code On FPGA?

I appreciate you in advance.

Best Regards
Amin Assar
Khaleghian, Mahdi Feb 22, 2011
Hi,
Please add this to RST state: datareadyack because datareadyack signal in DCT2D.VHD doesn't initialize.
Thanks,
Mahdi,

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