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the verilog code needs documentation #11
Closed ocghost opened this issue over 18 years ago
ocghost commented over 18 years ago

Sir, even though the full verilog code is available for the controller, it is still difficult to understand the code without any documentation.

vj_v1 commented about 17 years ago

Hi, could u provide me some assistance in the Implementation of the CAN controller, I require an internal block diagram for each block shown in the figure in this site. Could you help me somehow,

Also i require some assistance regarding the Hardware implementation of the CAN controller

Plz reply soon,

Thanks in advance.

vj_v2@yahoo.com

VJ

igorm commented about 17 years ago

SJA1000 from Philips will do the job.

igorm commented about 17 years ago

SJA1000 from Philips will do the job.

igorm commented about 17 years ago

For documentation take SJA1000 from Philips.

igorm closed this about 17 years ago
ocghost commented about 17 years ago

I do need the VHDL code for CAN controller .

from where can i get it???

I need it urgently....

Thanks in advance.

ocghost commented about 17 years ago

I do need the VHDL code for CAN controller .

from where can i get it???

I need it urgently....

Thanks in advance.

ocghost commented over 15 years ago

Hai ,,,,,, could u provide me some assistance in the Implementation of the CAN controller, I require an internal block diagram for each block shown in the figure in this site. Could you help me somehow, Also i require some assistance regarding the Hardware implementation of the CAN controller Plz reply soon, Thanks in advance.plz send me the details to chandravincent@gmail.com

aitortxo commented over 15 years ago

I have successfully simulated a transmitting frame. SJA1000 documentation helps a lot.

Page 61 shows steps to write a register (see lower part)

following those steps, some registers must be configured. 0) at the beginning, IP is in reset_mode. 1) set register 31 to define basicCAN or peliCAN 2) bus timing registers (6 and 7) if peliCAN 3) acceptance codes and masks (16 to 23) if peliCAN 4) leave reset_mode: register 0, with value 0 5) set register 16 to 28 with frame format (11/29 bit id) , remote_transfer/dataframe, data byte lenght with register(16), MSG id, and message data 6) now IP core is ready to send. Set register 1 with value 1 (TX_data)

My problem is that i can't make it work in an implemented design.

I can't even change the first register. I go to a state machine controlled by a pushbutton (this code is executed everytime button is pushed, incrementing int_cnt)

case (int_cnt) 4'd1: ale_i = 1'b1; 4'd2: data_to_port = rd_i ? 8'bz : 8'd31; 4'd3: ale_i = 1'b0; 4'd4: cs_can_i = 1'b1; 4'd5: data_to_port = rd_i ? 8'bz : 8'b11000100; 4'd6: wr_i = 1'b1; 4'd7: wr_i = 1'b0; 4'd8: begin cs_can_i = 1'b0; NewStep = 1'b1; end endcase

I have connected clkout_o to a pin to check freq with an oscilloscope, but it is changing 2*tclk, default value. So it is not changed actually.

Please, can anyone help me set register's value?

Thanks in advance Aitortxo.

abhijsh92 commented over 6 years ago

Hi,

Please provide documentation for register access with address and default values and also description on the design.

Please reply,

Thanks

email : abhinandanjsh@gmail.com


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