OpenCores

mdct - memory switching

Back to bugtracker overview.

Information:
Type :: BUG
Status :: OPENED
Assigned to :: nobody

Description:
signal "memswitchwr_s" in mdct.vhd needs to be delayed by two cycles, otherwise the last two outputs of DCT1D are written to the wrong memory because "memswitchwr_s" switches to early.

Comments:

Krepa, Michal Oct 3, 2012
Stephan,

I corrected the sources.

Thanks
Michal
berner, stephan Sep 28, 2012
bug caused corruption of the last row of each 8x8 DCT, only visible at high quality compression (I used 100%) and if high frequency content (e.g. sharp lines) is present in the image.
Krepa, Michal Sep 28, 2012
Hi Stephan,

Thanks for finding it. I will run simulation to observe it.

Michal
berner, stephan Sep 27, 2012
bug caused corruption of the last row of each 8x8 DCT, only visible at high quality compression (I used 100%) and if high frequency content (e.g. sharp lines) is present in the image.
berner, stephan Sep 27, 2012
Type your text here

Post a comment:
Login to post comments!

Back to bugtracker overview.

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.