I2C controller core

Hi Richard,

I am facing a problem where, during a sequential read of 6 bytes, the core automatically inserts the ACK-bit on the 9th bit for the first 4 bytes, then suddenly does not insert ACK-bit on the 5th byte.

This causes my SDA line to be held low, and arbitration-lost flag to be flagged high.. even though i had stopped my core.

1) Any idea why the core suddenly does not ACK the read-byte? My code is same for all the 6 bytes. 2) Any idea how to overcome this arbitration-lost flag?

Thanks & regards, Megan

Is the controller the only master on the bus? Something goes wrong with the communication. Seems like some other module is forcing SDA low, causing the arbitration lost.

I am using only 1 master and 1 slave. There is no other ongoing module to force the SDA low...

Hi Richard,

Now I zoomed in to the problem on the last byte read..

The master should clock on 8 SCL pulse (for the last byte read) + 1 SCL pulse for NACK. But what I am seeing is the wishbone core just clock out 8 SCL pulse and the SCL just stays high after that.

Any idea how to solve this problem?

That sounds wrong. Can you send me your testbench (or entire setup) in a private email. I will take a look.

Richard

I've sent you an email at your opencores.org mail account.. do take a look.. thanks!