NextZ80

I tried a simulation with Aldec's Active-HDL v9.3. If I assert and de-assert RESET, the simulation hangs with M1 & MEMRQ asserted and ADDR="xxxx". Without RESET it seems to run normally. Any suggestions?

Probably playing with the simulator settings will give you an insight. The simulation with XILINX ISE ISIM simulator, as the real FPGA implementation, have no this problem.