OpenCores

Porting this design and tb/sim for a Xilinx7 device using Vivado

Back to bugtracker overview.

Information:
Type :: REQUEST
Status :: OPENED
Assigned to :: nobody

Description:
Hi,

Has anyone already ported this design for Artix7 and used Vivado for sim & syn?

I am now stuck with the sim since the ip_32W_check/gen functionality is really creating a problem. I can't figure out how to replace this functionality with a Verilog file read as I don't fully understand what is being read into - 32bit data or packet-length or what!

One needs to keep a design and simu as generic as possible. The author should have also understood long ago that everyone will not use Cadence or Modelsim and that the EDA industry changes very fast!

Any leads on this issue will be helpful.

Thanks,
DP

Comments:

Paul, Debayan Jan 8, 2016
Another part to my question....

Has anyone tested this core with Xilinx Microblaze and used the files which the author has provided inside /trunk/EDK?

I would like to know if someone has run into strange problems in this type of functional verification flow.

Post a comment:
Login to post comments!

Back to bugtracker overview.

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.