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Status :: CLOSED
Assigned to :: sumanta, chaudhuri

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/:/ OC-team


Admin, OpenCores Jul 2, 2017

/:/ OC-team
Admin, OpenCores Jun 9, 2017
It moved to "others" as it is not a SoC core, and there is no "bus protocol" category.

/:/ OC-Team
chaudhuri, sumanta May 26, 2017
This project should be under bus protocol or system on chip blocks. I don't how did it end up in arithmetic cores ?
chaudhuri, sumanta May 26, 2017
This is an Avalon to WishBone Bridge. Avalon is a bus standard mainly used in Altera(Now Intel) Tools. Wishbone as every one knows is the open source bus protocol (circumvents all patents).

This bridge supports the wishbone B4 version, i.e it supports the use of ready signal, which makes the wishbone a pipelined bus. Wishbone B3 was not pipelined, i.e it can't emit requests unless the previous one has completed.

The configurable parameters of this bridge are Address Width, Data Width, Tag Width and the Max_Outstanding_Reqs which sets the pipelinability (how many requests can be in flight) of the bridge.

The RTL comes with a home made uvm testbench which I tested on modelsim. Any bug reported w.r.t this uvm testbench will e highly appreciated.

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