NextZ80

Good day!

I´m experiencing issues with CALL instruction. SP register (latch register as defined in line 71 of NextZ80Reg.v) contains 0xFF56. The CALL instruction is located at 0x128B. Return address is hence 0x128E. After reading the destination call address, I can see two write cycles, but the address to write to is 0xFFFF (for both writes). After that, SP register has the value 0xFFFF (instead of 0xFF54 as it should be).

I've tracked the offending behaviour down to a specific case statement in NextZ80Reg.v which assigns a value to mux_rdor. This case statement needs proper values, but you supply values with "x" bits, which is not acceptable. I´ve temporarily fixed it by changing the case into a casex statement, but I'm well aware that casex should be avoided by all means.

I guess all your "x" bits should be "?" bits instead, and use casez instead of casex when applicable.

I'm using iSIM with ISE 14.7 . The design uses the same WAIT pattern that you use for your example app.

Forget this "request". I tagged this bug as a request by mistake

You may replace the 'x' with '0' or '1',or use the "Post-Translate" simulation.