Synthesized module is too slow.

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Type :: BUG
Status :: OPENED
Assigned to ::

First of all great thanks for your work, it was very usefull.

1. I strongly recommend to change all "=" symbols to "Example: I've tried to implement as it is in Xilinx Spartan3 and final max speed was 5.3 ns, so about 188MHz, and requested a lot of iterations of router (Xilinx ISE 9.2.04i). Then I make it synchronous and acheived 3.9ns, 256MHz with about only 5 iterations. I think it is a max speed not for you module, but for Spartan3.

2. Also, I advice to make "reset" section of each register for correct simulation, synthes and implemented module operations. I've had some problems with initial values during simulations and in hardware too.

3. If you are interested in my corrections I can send you this changes via e-mail.
rng.v and top.v are fully tested in software.
rng.v is fully operational and correct also in harware.



sangal, ankur Apr 17, 2009
please send ur code
and wat would be the probability of repeating the numbers

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