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OR1200 should ignore cache control registers if no cache is present #53
Closed jeremybennett opened this issue about 15 years ago
jeremybennett commented about 15 years ago

I've observed that using cache control registers when no cache is physically present can lead to erroneous behavior.

I saw this when using GDB with ORPSoC built with no cache. Due to an error the embedded application enabled the instruction cache (bit 4 in the SR) even though it wasn't present. It did no other cache initialization.

A break point was set at location 0x1030. This substituted l.trap for the instruction already at 0x1030 (l.nop 4). The program was run to the breakpoint. The break point was then deleted, causing the l.trap instruction to be replaced by the original l.nop 4. All these code changes were via the ORPSoC debug unit.

On resumption the code continued to hit a l.trap instruction at 0x1030, even though a VCD showed that the instruction in memory was now l.nop 4. The VCD also showed that on resumption the instruction was not been re-fetched. Instead the CPU reused the old instruction (l.trap), which it had cached locally.

I believe this indicates a small problem in the cache implementation. The Architecture manual (intro to chapter 9) indicates that using cache registers when no cache is present should not halt the processor. Setting the enable bits in the SR didn't halt the processor in this case, but did cause "peculiar" behavior.

Jeremy

jeremybennett commented over 12 years ago
<p> Transferred to OpenRISC bugzilla (<a href="http://bugzilla.opencores.org/show_bug.cgi?id=5">Bug 5</a>). </p> <p> Marking closed. </p>
marcus.erlandsson was assigned over 12 years ago
jeremybennett closed this over 12 years ago

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marcus.erlandsson
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