Hi Everybody,
I've been working with or1ksim0.3.0 and found that if I set enabled=1 in sim.cfg "section ic", the ic is still not enabled. I took a look in the sources and found that in icache-model.c::ic_enabled() that only "cpu_state.sprsSPR_UPR |= SPR_UPR_ICP" was being set. In ic_simulate_fetch() however, cpu_state.sprsSPR_SR & SPR_SR_ICE is also being checked so I added a line to set ICE in ic_enabled().
cpu_state.sprsSPR_SR |= SPR_SR_ICE;
The simulator was now reporting IC read: 100% on all fetches. Looking further I found that in ic_end_sec() the line
memset (ic->tags, 0, ic->nsets ic->nways sizeof (oraddr_t));
however "0" is a valid tag which explains the 100% hit rate. I changed the memset value to "-1" so as to provide an initialized value of invalid for the cache. The results now appear to show initial access to a fetchaddr to fail, and subsequent access to addresses in the same block to succeed, and a reasonable hit rate.
John Alfredo