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AXI-to-Wishbone Bridge
by cassano on Jan 12, 2012 |
cassano
Posts: 1 Joined: Apr 28, 2009 Last seen: Oct 22, 2014 |
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Hi everyone,
I know there exists a PLB-to-Wishbone bridge in cores, but PLB has become a legacy bus standard according to Xilinx tools and will not be supported starting with the 7-Series FPGA's. I think it is the same case for Altera also. Is there a AXI-to-Wishbone bridge project in planning? |
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RE: AXI-to-Wishbone Bridge
by refugee on Jul 20, 2012 |
refugee
Posts: 2 Joined: Mar 25, 2010 Last seen: Jul 22, 2020 |
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Hi,
really interesting post, I truly wonder why nobody else has referred to an AXI-WB Bridge so far. FYI, I found some sort of implementation @ https://bitbucket.org/danstrother/dls_cores/src/cd729848a35b/axi/ - I haven't yet had the chance to take a look at it, but it's a start nevertheless. Would be nice if we kept in touch on any update regarding this particular issue! :-) Regards, David |
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RE: AXI-to-Wishbone Bridge
by jorge.echavarria on Jun 9, 2015 |
jorge.echavarria
Posts: 1 Joined: Sep 4, 2013 Last seen: Jun 26, 2019 |
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Hi,
I am really interested in this bridge, have you found anything yet? |
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RE: AXI-to-Wishbone Bridge
by dgisselq on Jun 9, 2015 |
dgisselq
Posts: 247 Joined: Feb 20, 2015 Last seen: Jul 15, 2022 |
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Have you taken a look at Dan Strother's code at all yet? It looks like there's an AXI master to WB slave interface in there. Does that meet your needs?
Dan |
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RE: AXI-to-Wishbone Bridge
by brent.nolan on Sep 20, 2017 |
brent.nolan
Posts: 3 Joined: Apr 22, 2016 Last seen: Jun 29, 2020 |
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Here's links to two AXI to Wishbone implementations. One is on OpenCores and the other is Dan's 2011 implementation.
Dan Stother's code: https://bitbucket.org/danstrother/dls_cores/src/beb677ea1919ea2cec984426e1f8d89ec21b03a7/axi/rtl/dlsc_axi_to_wb.v OpenCores AXI to WB Project by Adrian Byszuk and Wojciech Zabolotny: https://opencores.org/project,ax4lbr -- GitHub repo is at https://github.com/wzab/vextproj |
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