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Verilog code for DDR SDRAM Controller Core
by sumanthhr on Apr 2, 2013 |
sumanthhr
Posts: 5 Joined: Mar 20, 2013 Last seen: Apr 17, 2015 |
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Hi,
I need Verilog code for this project"DDR SDRAM Controller Core". I went through opencores project section it has code written in VHDL. |
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RE: Verilog code for DDR SDRAM Controller Core
by aikijw on Apr 2, 2013 |
aikijw
Posts: 76 Joined: Oct 21, 2011 Last seen: Jul 8, 2023 |
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Well then... Port it...
Hi,
I need Verilog code for this project"DDR SDRAM Controller Core". I went through opencores project section it has code written in VHDL. |
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RE: Verilog code for DDR SDRAM Controller Core
by sumanthhr on Apr 5, 2013 |
sumanthhr
Posts: 5 Joined: Mar 20, 2013 Last seen: Apr 17, 2015 |
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Well then... Port it...
Port it ? what does it mean. can you please help me to convert vhdl to verilog. any good free translator[windows user] |
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RE: Verilog code for DDR SDRAM Controller Core
by syedshan on Apr 5, 2013 |
syedshan
Posts: 2 Joined: May 25, 2010 Last seen: Apr 27, 2013 |
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by port it he means that make a module in verilog, which only serves as top level module and inside of which you instantiate the VHDL module as if it is verilog module e.g.
entity VHDLA is port( ... ); end entity; ... now Verilog module is like this... module toplevel_ver( .. .. ); regs, wires, //make instantiations VHDLA insta (connections); hope this helps |
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RE: Verilog code for DDR SDRAM Controller Core
by hellwig on Apr 5, 2013 |
hellwig
Posts: 32 Joined: Dec 30, 2007 Last seen: Nov 3, 2022 |
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No, it isn't; what you describe is called "wrapping". In contrast to that, "porting" means re-writing in another language or for another environment. This is NOT an automatic task; you have to understand what the circuit is doing and how it works - then you formulate what you explored in the target language.
Hellwig |
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RE: Verilog code for DDR SDRAM Controller Core
by syedshan on Apr 5, 2013 |
syedshan
Posts: 2 Joined: May 25, 2010 Last seen: Apr 27, 2013 |
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Ah ok...
I understand... But wrapping is much easier than porting and convinient as well You see I was once doing something and made my code in verilog, later I know the kit that I will be working on has other suporting(like PCIe, router etc) in vhdl. Hence I did wrapping and my code was VHDL outside, and verilog inside |
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RE: Verilog code for DDR SDRAM Controller Core
by letmein on Apr 7, 2013 |
letmein
Posts: 2 Joined: Nov 29, 2011 Last seen: Jan 16, 2015 |
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What everyone is missing is that some environments can't deal with combined language code. If you are synthesizing, almost all tools that I know of can deal with both. This isn't so with some simulators. If you are using Opensource tools, they don't handle mixed language simulation yet.
Commercial tools like QuestaSim (Mentor), or Incisive(Cadence) can do this - but it costs extra to support both VHDL & Verilog. You might try the Xilinx simulator. It'll handle both languages. |
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RE: Verilog code for DDR SDRAM Controller Core
by aikijw on Apr 7, 2013 |
aikijw
Posts: 76 Joined: Oct 21, 2011 Last seen: Jul 8, 2023 |
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LOL... It's pretty likely that his class requires that projects be submitted in Verilog... If he submits in VHDL, I'd bet his instructor would be a bit suspicious that he hadn't done his own work... :-) Just a guess... About 98% of the time, when someone comes here and makes the statement "give me " it's because they waited until the end of term to start a project that probably should have been started 4 months ago, and they're looking to snag some free assistance which they can then trade in for a grade... When I was in school (assuming that this is the original poster's purpose), this was called cheating, and if you got caught, you'd get your backside hauled to the Dean of Engineering's office, and/or Honor Court... God help you if you got caught twice... Unfortunately, the world has changed a good deal in 15 years...
YMMV... This may not have been the original poster's intent... Only the OP knows...
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RE: Verilog code for DDR SDRAM Controller Core
by kenpillay on Apr 27, 2013 |
kenpillay
Posts: 2 Joined: Feb 28, 2013 Last seen: Jun 9, 2015 |
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Any thoughts as to why Steve Ecob's implementation in verilog would not do the job?
http://opencores.org/project,ddr3_sdram DDR3 SDRAM controller |
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RE: Verilog code for DDR SDRAM Controller Core
by SANTOSH_L on Nov 18, 2013 |
SANTOSH_L
Posts: 1 Joined: Sep 24, 2013 Last seen: Apr 15, 2015 |
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Hi,
I need Verilog code for this project"DDR SDRAM Controller Core". I went through opencores project section it has code written in VHDL. |
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RE: Verilog code for DDR SDRAM Controller Core
by rajeev_v on Jan 27, 2014 |
rajeev_v
Posts: 14 Joined: Oct 11, 2012 Last seen: Apr 5, 2017 |
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can any one give me this code that you have
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RE: Verilog code for DDR SDRAM Controller Core
by onkar123 on Nov 7, 2017 |
onkar123
Posts: 1 Joined: Oct 31, 2017 Last seen: Nov 9, 2017 |
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Hi,
I need Verilog code for this project"DDR SDRAM Controller Core". I went through opencores project section it has code written in VHDL. |
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RE: Verilog code for DDR SDRAM Controller Core
by dgisselq on Nov 8, 2017 |
dgisselq
Posts: 247 Joined: Feb 20, 2015 Last seen: Jul 15, 2022 |
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RE: Verilog code for DDR SDRAM Controller Core
by aikijw on Nov 10, 2017 |
aikijw
Posts: 76 Joined: Oct 21, 2011 Last seen: Jul 8, 2023 |
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It'd be a lot easier if they'd just post the class syllabus and project assignment... ;-)
Ahhhhhhh... November... When the desperation begins to set in... /jw |
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RE: Verilog code for DDR SDRAM Controller Core
by zhangguozhong on Dec 27, 2017 |
zhangguozhong
Posts: 1 Joined: Dec 26, 2017 Last seen: Apr 14, 2018 |
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Hi,
I need Verilog code for this project “ ddr2 sdram controller core ”.Can anyone give me this VDL code that you have |
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