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LLVM for OpenRISC: Euro-LLVM 2012 workshop by Anton Korobeynikov

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LLVM for OpenRISC: Euro-LLVM 2012 workshop by Anton Korobeynikov by jeremybennett on Apr 14, 2012			jeremybennett Posts: 815 Joined: May 29, 2008 Last seen: Jun 13, 2019
<p> As some of you know, I spent the last two days at the Euro-LLVM conference in London. The final event was a workshop "Building a backend in 24 hours" given by Anton Korobeynikov. Anton used the OpenRISC as his example processor, based on work he carried out on 5/6 April. His work can be cloned from GitHub at </p> <ul> <a href="https://github.com/asl/llvm-openrisc.git">https://github.com/asl/llvm-openrisc.git</a> </ul <p> The changes can be seen by a git diff against git commit 9751b81fc97dcb6ecc4be4304ef8e6e8cf79f6e4, the point at which he branched from the main tree. </p> <p> As promised, this is my short summary of the presentation. The slides and I believe video will be available shortly through the LLVM website: </p> <ul> <a href="http://llvm.org/devmtg/2012-04-12/">http://llvm.org/devmtg/2012-04-12/</a> </ul> <h2>OVERVIEW</h2> <p> Anton started by outlining the levels at which target specific code can be introduced <ul> <li>LLVM IR passes</li> <li>Selection DAG (SDAG) passes</li> <li>MI passes</li> <li>MC streamers</li> </ul> </p> <p> LLVM IR passes <ul> <li>some things easier to do here</li> <li>can simplify codegen</li> <li>safer (more fixed pass order)</li> </ul> </p> <p> SDAG passes<ul> <li>first strictly backend IRâ��lower level than LLVM IR</li> <li>built on a per-BB basis</li> <li>concludes with instruction selection</li> </ul> </p> <p> MI passes<ul> <li>register allocation</li> <li>yet another sort of IR</li> </ul> </p> <p> MC streamers<ul> <li>lower MI level to MCInst</li> <li>let the MC streamers decide what to do next</li> </ul> </p> <p> Customization<ul> <li>can add own passesâ��e.g. for delay slot filling</li> </ul> </p> <h2>BACKEND DETAILS</h2> <p> <ul> <li>standalone library</li> <li>C++ and TableGen <ul> <li>TableGen is domain specific language to specify <ul> <li>reg sets</li> <li>calling conventions</li> <li>instruction patterns </ul></li> </ul></li> <li>inheritance and overloading are used to add target specific bits</li> </ul> </p> Stub Backend </p> <p> Q: what is needed to do nothing.<br /> A: quite a lot <ul> <li>15 classes</li> <li>1KLOC c++ and TableGen</li> <li>15 key classes to be defined</li> </ul> </p> <h2>EXAMPLE: OPENRISC</h2> <p> Goal to process a trivial LLVM IR fragment </p> <p> Steps: <ul> <li>add or32 as target triple</li> <li>implement the 15 stub classes</li> <li>define all regs and classes</li> <li> define calling convention</li> <li>implement hooks <ul> <li>copying physical regs, prologue/epilogue etc</li> </ul></li> <li>add standard boiler plate</li> <li>implement LowerFunctionArguments <ul> <li>non-trivial: look at MSP 430 for example</li> </ul></li> <li>convert MI to MC (straightforward)</li> <li>MCInst printing (also straightforward)</li> <li>add first instruction: function return <ul> <li>add pattern</li> <li>note branch delay TODO</li> </ul></li> </ul> </p> <p> Adding Clang <ul> <li>to write testcases in C</li> <li>provide TargetInfo for binutils-ish tool chain</li> <li>detailed tool chain description done later</li> </ul> </p> <p> Next steps <ul> <li>reg-reg arithmetic</li> <li>load/store: match address modes</li> <li>proper function frames</li> <li>delay slot filling</li> <li>branch folding</li> <li>â�¦</li> </ul> </p> <h2>Q&A</h2> <p> I asked how long it would take to complete the implementation, so that reasonable swathes of complex C/C++ could be compiled. Apparently the MSP 430 took him 3 weeks working evenings and weekends. Longer for a non-expert of course. </p> <p> Hope this is useful. Full detail from the website above when the slides and video become available. </p> <p> Jeremy </p> <p> -- <br /> Tel: +44 (1590) 610184<br /> Cell: +44 (7970) 676050<br /> SkypeID: jeremybennett<br /> Email: <a href="mailto:jeremy.bennett@embecosm.com">jeremy.bennett@embecosm.com</a><br /> Web: <a href="http://www.embecosm.com">www.embecosm.com</a> </p> As some of you know, I spent the last two days at the Euro-LLVM conference in London. The final event was a workshop "Building a backend in 24 hours" given by Anton Korobeynikov. Anton used the OpenRISC as his example processor, based on work he carried out on 5/6 April. His work can be cloned from GitHub at https://github.com/asl/llvm-openrisc.git The changes can be seen by a git diff against git commit 9751b81fc97dcb6ecc4be4304ef8e6e8cf79f6e4, the point at which he branched from the main tree. As promised, this is my short summary of the presentation. The slides and I believe video will be available shortly through the LLVM website: http://llvm.org/devmtg/2012-04-12/ OVERVIEW Anton started by outlining the levels at which target specific code can be introduced LLVM IR passes Selection DAG (SDAG) passes MI passes MC streamers LLVM IR passes some things easier to do here can simplify codegen safer (more fixed pass order) SDAG passes first strictly backend IRâ��lower level than LLVM IR built on a per-BB basis concludes with instruction selection MI passes register allocation yet another sort of IR MC streamers lower MI level to MCInst let the MC streamers decide what to do next Customization can add own passesâ��e.g. for delay slot filling BACKEND DETAILS standalone library C++ and TableGen TableGen is domain specific language to specify reg sets calling conventions instruction patterns inheritance and overloading are used to add target specific bits Stub Backend Q: what is needed to do nothing. A: quite a lot 15 classes 1KLOC c++ and TableGen 15 key classes to be defined EXAMPLE: OPENRISC Goal to process a trivial LLVM IR fragment Steps: add or32 as target triple implement the 15 stub classes define all regs and classes define calling convention implement hooks copying physical regs, prologue/epilogue etc add standard boiler plate implement LowerFunctionArguments non-trivial: look at MSP 430 for example convert MI to MC (straightforward) MCInst printing (also straightforward) add first instruction: function return add pattern note branch delay TODO Adding Clang to write testcases in C provide TargetInfo for binutils-ish tool chain detailed tool chain description done later Next steps reg-reg arithmetic load/store: match address modes proper function frames delay slot filling branch folding â�¦ Q&A I asked how long it would take to complete the implementation, so that reasonable swathes of complex C/C++ could be compiled. Apparently the MSP 430 took him 3 weeks working evenings and weekends. Longer for a non-expert of course. Hope this is useful. Full detail from the website above when the slides and video become available. Jeremy -- Tel: +44 (1590) 610184 Cell: +44 (7970) 676050 SkypeID: jeremybennett Email: jeremy.bennett@embecosm.com Web: www.embecosm.com

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