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ALTERA TRANSCEIVER PHY CUSTOM
by clive.seguna on Oct 30, 2016 |
clive.seguna
Posts: 2 Joined: Feb 20, 2016 Last seen: Dec 28, 2021 |
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Dear All,
Does someone have example project using Cyclone V FPGA transceiver to simply transmit and receive 16 bits of parallel data read from FPGA fabric trough a transcever ? At the moment I have issues with word alignment and cannot figure it out from datasheet. Not easy to interpret. Thanks. Regards CS |
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RE: ALTERA TRANSCEIVER PHY CUSTOM
by dgisselq on Oct 31, 2016 |
dgisselq
Posts: 247 Joined: Feb 20, 2015 Last seen: Jul 15, 2022 |
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Sorry. I could help you with Xilinx, but not Altera.
Others on the forum might know Altera better.
Dan |
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RE: ALTERA TRANSCEIVER PHY CUSTOM
by clive.seguna on Nov 2, 2016 |
clive.seguna
Posts: 2 Joined: Feb 20, 2016 Last seen: Dec 28, 2021 |
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Do have Xilinx sample VHDL ? Maybe I try to correlate.
Don`t know if anyone can maybe help on ALTERA. Thanks. Regards, Clive |
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RE: ALTERA TRANSCEIVER PHY CUSTOM
by dgisselq on Nov 3, 2016 |
dgisselq
Posts: 247 Joined: Feb 20, 2015 Last seen: Jul 15, 2022 |
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Clive,
None of my examples are working (yet). I would've known where to point you in the Xilinx reference manual, though!
Dan |
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RE: ALTERA TRANSCEIVER PHY CUSTOM
by Jshaffer on Jun 23, 2017 |
Jshaffer
Posts: 1 Joined: Mar 14, 2012 Last seen: Jan 29, 2020 |
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Are you receiving coherent data? I can recall there being an issue when I first got the transceiver running on a Cyclone V gt. The Cyclone V transceiver PHY was easier to set up, from what I remember.
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