A 2-D IDCT Architecture without Memory Registers For Multiple Video Standards


We have proposed a low-cost VLSI

architecture of a multistandard IDCT in this

brief. IDCTs of several standards are integrated

in the proposed architecture. The circuits are

efficiently shared and saved based on the FS and

AS strategies. It can be concluded that a high

decoding capability is achieved in small. Finally

a new fully parallel architecture based on row-

column decomposition has been proposed for

the computation of the 2D DCT. The system

involves no memory transposition, and is highly

modular and utilizes a highly parallel structure

to achieve high-speed performance. Due to

its widely identical units, it will be relatively

easy to implement and very suited to VLSI

implementation. It uses two identical units

for the computation of the row and column

transforms and arrays of shift registers to

perform the transposition operation. the proposed

architecture achieves the same throughput rate at

much lower hardware cost and communication

complexities. It is also worth mentioning that in

the proposed design, the same architecture can

be used for the computation of both the forward

and the inverse 2D DCT.

By: swami, nathab

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