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Coding guide lines at OpenCores

To ease reusablity OpenCores has decided upon a common structure for IP cores. This makes it easier for end users to quickly adopt IP cores from the community.


Promote your project - write a good description

Confidence and first-impression is two important items that a project at OpenCores must deliver to an engineer before he/she decides to use it. . It is therefore very important that the project includes a complete design package, but to start with you have to have a good description of your project.


Update from OC-Team

- page-cache-function
- replaced broken hard-drive
- started to "cleanup" the project-list
This topic gives you an update of what has been "cooking" at the OpenCores community during the last month.


Updated and new IP-cores

View a list of some of the projects that has been updated during the last month. Here you will also see interesting new projects that have reached a first stage of development.
This month we present 2 new projects & 5 updated


Lennart Lindh makes the FPGA shine

Interview with Lennart Lindh, professor working with FPGA Technology for Research and Education.


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Newsletter September 2009

Coding guidelines at OpenCores.

To ease re-usablity OpenCores has decided upon a common structure for IP cores. This makes it easier for end users to quickly adopt IP cores from the community.

Modeling guidelines
It is important that all cores at OpenCores has a common “look and feel”. This includes documentation, directory structures of source code and documents, interfaces used (especially using the preferred system interconnect bus Wishbone).

Specification Document
Before you jump into HDL coding, try to check existing cores and write a specification document. This will have several advantages:

  • clear definition of what the core should do and which standards will be supported
  • defines profiles of developers for formation of a team

Essentially the core is a black box, and the specification documentation should only be concerned with the interface to this black box. Anyone wishing to use the core should only have to read the specification document while those wishing to modify or add to the core should read design document as well.

Directory structure
On OpenCores we have decided upon a common directory structure outlined below.

Coding guide lines,

This simplifies for anyone to evaluate and use the core within a design.
To include simulation and synthesis scripts also eases evaluation of cores. A synthesis script clearly outline exactly how the design is synthesized. Even if the end user does not have the same synthesis tool the script is a good starting point when porting the build environment. For simulation the use of open source simulators available for everyone is highly encourage. Good examples of open source simulators are Icarus ( and GHDL ( Note that in Ubuntu Linux both of these simulators are available via packege manager apt-get. Independent of simulator used for test cases try to include simulation scripts.

For details regarding naming conventions, preferred syntax usage, etc see the OpenCores HDL modeling guidelines.

Also the use of advanced standalone preprocessor can enhance the re-usability with better adoptation of cores for different implementations. A typical use of a preprocessor is to include control register for a SDRAM memory controller when used in an ASIC target but have the exact behavior defined at synthesis time for FPGA targets. Usage of preprocessor is commonly used for Verilog designs but the usage of a stand-alone preprocessor is equally applicable to VHDL. Again installation in Ubuntu Linux is easy. Verilog Preprocessor: sudo apt-get install vbpp Verilog PERL Preprocessor: cpan install Verilog::Language

The importance of “good” project information

One of the great benefits with open-source IP cores is that the verification is shared with thousands of engineers from all over the world, which allot of engineers are aware of. It is however extremely important that also the rest of the "project-items" are "up-to-date" and available. Confidence and "first-impression" are two important items that a project at OpenCores must deliver to an engineer before he/she decides to use it. It is therefore very important that the project includes a "complete" package, meaning:

  • Well structured RTL code
  • Self checking Testbench
  • Makefile that starts simulation (with preferably Icarus or GHDL scripts)
  • Documentation
  • General information (RTL size & speed using different FPGA’s, how the cores are being used etc.)

Each project contains four standard pages per default, these are:

  • Overview
  • News
  • Downloads
  • Bugtracker

Overview page
This page contains generic information about the project (dates, project properties, maintainers). It has also got an important block called “Description”. The text in this block is a "meta description"-tag and the first 160 characters will be visible at Goggle’s search-list, so it’s important that you describe your project in a short and understandable way.
More text-blocks can be added to the Overview-page and it is recommended to add a "design-block-schematics", a pictures says more then thousands of words.

News page
Whenever the project is updated a mandatory “update”-question will occur, make sure that an understandable note is entered. Once again it’s important to be able to track all changes, not only the RTL changes. It is also possible to add “news text” manually on this page.

Downloads page
This page contains multiple items, it might show “files” from the old OpenCores website. These files were never added into CVS at that time and are now located here and in SVN under “web_uploads”.
This page also contains pictures and/or documents. The purpose with these pictures/documents are to be used on the other pages, for example on the Overview-page. The “Embedd-tag”-text provides the link to be used on other pages.

All bugs and requests should be reported back into the Bugtracker system. It’s very important that we all help the maintainer/s with the verification and especially reporting back any identified bugs.

It is also possible to add additional pages to the project, but remember to make the project as “easy and understandable” as possible.
Please help us with making OpenCores even better and to increase the quality and creditability of the projects!

Since the complexity of hardware functions has increased significantly, the verification is increasing exponential. This problem makes open-source methodology the only solution to handle future hardware development, meaning sharing the enormous verification effort needed.

Update from OC-Team

This topic gives you an update of what has been "cooking" at the OpenCores community during the last month.

This month activities:

Website information:
Added page-cache-function to project-list-page (performance improvement).

Server information:
Replaced broken hard-drive. No data was lost due to HW-RAID5 disk configuration.

Our message to the community:

  • Help us find incomplete or obsolete projects
    We have now started task to "cleanup" the project-list on OpenCores, meaning that we want to "mark" incomplete obsolete projects with a "not ready"-sign. This will make it easier for all users to find suitable projects and hopefully also motivate the project maintainer to complete the project. So please send us an email with incomplete projects!
  • Update your project with the latest information
    Please go through your projects at OpenCores and update it/them with the latest information. Make sure that all needed documentation (including “readme”-files) is uploaded. If the testbench isn’t “self-checking”, please add this features (it’s very important).

Updated and new IP-cores

View a list of some of the projects that have been updated during the last month. Here you will also see interesting new projects that have reached the first stage of development.


Scratch DDR SDRAM Controller
DDR SDRAM controller core targeted at the mt46v32m16 chip on the Spartan3e Starter Board. The testbench synthesizes and runs on the targeted hardware. Additionally I've integrated this controller core into an SoC design consisting of a T80 soft cpu with a VGA controller.
Development status: Beta
Sep 22, 2009 Checked in fixes after integration and testing with a T80 CPU
Sep 13, 2009 Integrated the Scratch SDRAM controller into my own SoC project successfully.
Sep 12, 2009 Updated the description

The Minimal System on Chip is a System-on-Chip (SoC) implementation with standard IP Cores available at OpenCores. This implementation is composed by a standard project, comprehending the standard IP Cores necessary for a SoC embedding the OpenRISC implementation or1200.
This project idea is to offer a SoC, which can be uploaded to every FPGA and be compatible with every FPGA board, without the requirement of changing its code. In order to deliver such a project, the project has been based on a standard memory implementation and the Advanced Debug System, which allows system debug with the same cables used for FPGA configuration.
The adaptation of the project to a target board is made in 2 steps maximum. First the minsoc_defines.v file has to be adjusted, generally one has to only uncomment his FPGA manufacturer and FPGA model definitions. After that a constraint file for your specific pinout has to be created. There are constraint files for standard boards also, in the backend directory of the project.
Furthermore the project offers for this same SoC a working testbench and firmwares. The actual testbench can be run out of the box using Icarus Verilog v. 9.1. The firmwares are nearly the same of those of orpsoc_v2. The differences are for now, that the known uart "hello world" example now runs with interrupts and a new Ethernet example has been added to it.
To complete, the size of the standard memory of the implementation can be adapted to your needs/possibilities by defining its address width inside of the same minsoc_defines.v file.
Development status: Beta
Sep 18, 2009: Project description.
Sep 18, 2009: publishing the project


Just Another Ray Tracer
This is a hardware sphereflake ray tracer. It's been made for ray tracing learning purposes along with my masters degree thesis development. The whole work began back in february 2009. There's a lot of work done along with the codes published here, for example, there is a ray tracer profiler/simulator done in C, also a plugin for Blender3d in order to make 3d models for the project and also a report maker in order to gather profiling results. The architecture described in these files would NEVER be achieved without that previous work.
Development status: Alpha
Updates: Uploaded the block to connect the dot product calculation cells.

Simple AES3 / SPDIF receiver
AES3 / SPDIF receiver is simple, minimalistic but powerful core which decodes biphase mark coded AES3 compatible signal and retransmits it in I2S-like format. Audio words are coded in 2's complement format, however, in contrast to I2S, they are LSb and not MSb aligned and all auxiliary bits of AES3 are left unchanged and transmitted together with audio word. There is even some mess in first four bits of each word as result of preamble detection. Nevertheless, this core can be implemented on XC9572XL-5 with only 43 macrocells utilization and fmax around 100MHz while capable of receiving AES3 at fs = 96kHz with clk at 50MHz.
Development status: Stable
Update: Fixed previous fix - removed redundant bbbr_shift_reg_proc.

The Xgate Co-processor Module, Xgate, is a 16 bit programmable RISC processor that is managed by a host CPU to reduce the host load in handling interrupts. Because the Xgate is user programmable there is a great deal of user control in how to preprocess data from peripheral modules. The module may be configured as a simple DMA controller to organize data such that the host only deals with whole messages and not individual words or bytes. The Xgate may also deal with higher levels of messaging protocols than the peripheral hardware recognizes. Encryption algorithms are also supported by the instruction set.
Development status:
Sept 1, 2009: This is a prerelease checkin and should be looked at as an incremental backup and not representative of what may be in the final release. RTL - 75% done What works: Basic instruction set execution simulated and verified. Condition code operation on instructions partially verified. Basic WISHBONE slave bus operation used, full functionality not verified. What's broken or unimplemented: All things related to debug mode. WISHBONE master bus interface. User Documentation - 30% done
Sept 10,2009: Added WISHBONE master bus submodule and some related top level signals but still not much real functionality. Added code to allow for memory access stalls. Upgraded testbench to insert memory wait states. Added more error detection and summery. Improved instruction decoder. Still needs more work to remove redundant adders to improve synthesis results.

The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog. It is compatible with Texas Instruments' MSP430 microcontroller family and can execute the code generated by an MSP430 toolchain in a cycle accurate way.
The core comes with some peripherals (GPIO, TimerA, generic templates) and a Serial Debug Interface for in-system software development.
Development status: Stable
Sep 20, 2009 Windows Users: Some batch files have been created so that you can now run the FPGA Xilinx flow from windows (assuming that ISE is installed on your system).
Aug 30, 2009 The defines are now directly included (with the `include construct) in the Verilog files.
Aug 30, 2009 replaced "" with "openMSP430_defines.v"

Interview with Lennart Lindh, professor working with FPGA Technology for Research and Education.

Professor Lennart Lindh has had his focus on programmable logic for over 20 years. He wants to throw out the present von Neumann architecture and replace it with FPGAs that can handle data in parallel and with much less overhead. The switch would cut back cost and also reduce the development time compared to today's embedded systems with processors and tangled code.

- The unique thing with FPGAs is that the development continues so rapidly, which makes the price go down all the time for boards, components and tools. It is really incredible and thats the reason why I and many others will continue to work with FPGAs, says Lennart Lindh.

He is a veteran of the programmable logic and an all-rounder who likes to start new projects. The base has for a long time been Mälardalens University, where he has built up both education and research. But since a year ago, he is a professor in Jönköping where he was born.

In addition to the professorship, which is half-time, he tries to educate the industry, writes books and organizes the conference FPGA World. He also likes to spends November and part of December, far from the darkness and gloomy weather in Sweden.

Building blocks boost productivity
When I meet him a rainy summer day in Västerås where he still lives, he talks passionately about today's component-based design methods, where you can take complete IP blocks, much like when you buy a door or window to a house-building, instead of writing all the code from scratch. The component-based thinking has been a major productivity boost for both software and hardware.

- But you must know what you're doing. Even inserting a door has its problems at a lower level of abstraction. Many business leaders believe they can work only on the higher abstraction levels, it is completely wrong. If we get that type of students in classes in embedded systems, then there is a risk that you get problems that causes delays and extra costs. Engineering skills are incredible important and you do not learn that college but rather in the industry.

At the same time the component-based way of thinking is an opportunity for Swedish companies.

- The things the companies want to keep as secrets, they can design as a component, like a black box.

But few Swedish companies have taken the opportunity to earn money selling components. Some exceptions exists like Mocean Labs who developed a Most-block for Xilinx library. Also a few consultant companies like ORSoC, BitSim and Prevas has some components. In addition, Xilinx does part of the development of its soft processor MicroBlaze in Sweden, so the knowledge of component based design exist in the country.

- There is an opportunity for more companies. FPGA-companies as Xilinx and Altera have similar frameworks to manage hardware and software components so as a component supplier you can sell through them.

In addition, the job only has to be done once if you write the code in VHDL and do not use special functions.

- If you follow certain design rules you can synthesize VHDL code for a new FPGA-circuit an indefinitely number of times and even transfer the design to an ASIC.

Lennart Lindh, however, believes that more research is needed on how to do design on a combination of software and hardware to get the entire design to be independent of the technology. For each new generation, the code has to be recompiled, but the functions and timing behavior of the component will not change.

If we get there, the hardware is at the same abstraction level as the software is today. If you have written a program in C you should be able to move it to a new processor and get the same functions, the only problem is that the time-behavior may change.

In 1999 Lennart Lindh started Real Fast, a company involved in training and consultancy. The company also sold IP components. It was a real-time kernel and an UDP hardware acceleration originated from research at Mälardalen University. The business was sold in 2006 and 2007.

- I felt shattered by running a company. A lot of the work is not about technology, and in the end you have to choose what you want to do. Both worlds are fun but I prefer to work with technology and it suits me better to be at the academy.

Through his own company Agstu he remains involved with training for the industry.

- If you have done research, you should train people and also write books about the new knowledge. Otherwise, it falls into oblivion and then all the research money is wasted.

All the course materials for industry and for students at Bergen University College, Mälardalen University and the Jönköping University are the same. But teaching methods are different.

- Those who come from the industry has often worked with FPGAs for some years, they have a more solid knowledge. Some even know more than me in certain areas, which leads to interesting discussions.

The lab fits in the portfolio
Lennart Lindh tries to spend November and December in warmer countries than Sweden. A couple of years he has been in India and Thailand but also in the Canary Islands.

- It's fantastic, really something I can recommend if you have the possibility. It gives so many side effects, with new contacts and the possibility to work undisturbed. A few times I've been invited by the university. Other years, I write books and do research. I have my FPGA-board, a computer and the Internet. That's is my entire lab.

Lennart Lindh's view on the Internet changed when he was a member of a research project which did development for Mentor Graphics. The project had members from United States, England and India. Cooperation run smoothly with weekly virtual meetings over the Internet and by exchanging reports.

The same technique could be used to connect the few, scattered FPGA-researchers in the Nordic countries.

- It's a vision I have, that the Universities don't work independently, but rather work together, but it requires money and I do not know if we can get funding for it.

Has created a meeting place
The FPGA World Conference, which he started with David Källberg five years ago is the embryo of a Swedish network for programmable logic. FPGA World has since the start, in Västerås in the autumn of 2004, grown to become an established event which annually brings together approximately 200 FPGA-professionals. This fall, the conference and its associated mini-exhibition also takes place in Copenhagen and the status of the academic part has been increased. The accepted academic papers are published by the sub-department Sigbed, within the research organization ACM.

Lennart Lindh would also like to try to forge closer ties with the FPGA-companies.

- It would be good to have a connection with San José. Now that I have good contacts with Altera I'll try to get a foothold in their research lab so I can send the graduate students over there.

As we all know the two major FPGA companies have a continuously ongoing duel, but the fact that Lennart Lindh nowadays mostly work with Altera is not to bee seen as a position in the match.

- I had worked a long time with Xilinx, so I switched because I wanted to broaden my views.

Request more support from industry
Most FPGA manufacturers have an extensive program to help universities. Among other things the give the students their own development boards and they can download free tools for development. Altera has also arranged special student competitions and announce the winners at the FPGA World conference.

- I would be happy to see more FPGA suppliers support the interest among young people to learn more about the FPGA technology.

Despite contests and other gimmicks, the interest for hardware among students is very weak. In fact so weak that the information technology courses that Lennart Lindh created at Mälardalen University has folded. What remains is simply the software group.

- The larger universities have fared better and Engineering continues to attract students to the electronics and embedded systems, although there are not as many as in the 90s.

In Jönköping, he is planning to build a small research group that will have a large network to the best research environments around software/hardware for embedded systems.

- Of course I will continue with accelerators for operation system with entirely new functions that are not possible to implement in software alone. But the orientation depends on what the sponsors want, I myself would like to investigate how to make complex embedded systems, without von Neuman Architecture.

The idea is to examine the design methodology and techniques to make embedded systems exclusively in hardware, without any processor cores but also systems with a combination of software and hardware.

Sooner or later, there will be a change of the system
It was proven by one of his graduate students in the early 2000s. Four out of five embedded systems such as ABB used, were possible to make cheaper and with decreased development time, by dropping the CPU and only use a FPGAs without any hard or soft processor cores.

The solution is perhaps comfortable when you develop an embedded system for a coffee machine but not that obvious for larger systems. Lennart Lindh is worried that Swedish companies are too conservative, they believe that software is the technology front for embedded systems.

- It's quite clear that there will be changes in technology, we must constantly be alert. As hardware costs approach zero we must concentrate on the development cost.

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